Abstract: A metal gate transistor includes a substrate, a metal gate on the substrate, and a source/drain region in the substrate adjacent to the metal gate. The metal gate includes a high-k dielectric layer, a bottom barrier metal (BBM) layer comprising TiSiN on the high-k dielectric layer, a TiN layer on the BBM layer, a TiAl layer between the BBM layer and the TiN layer, and a low resistance metal layer on the TiN layer.

Abstract: A method of manufacturing a semiconductor device comprises providing a carrier, disposing a plurality of dies over the carrier along a first direction and a second direction orthogonal to the first direction to arrange the plurality of dies in a plurality of rows, and shifting one of the plurality of rows along the first direction or the second direction in a predetermined distance.

Abstract: A light-emitting element includes: a light transmissive substrate having a first main surface, a second main surfaces, a first lateral surface, a second lateral surface, a third lateral surface, and a fourth lateral surface; a semiconductor layered body; a first light reflection member; and a second light reflection member. A cross-sectional plane of the light transmissive substrate perpendicular to the first main surface and intersecting with the third lateral surface and the fourth lateral surface has a first concave figure having a first recess. The deepest portion of the first recess is arranged on an inner side of an outer periphery of the semiconductor layered body. The third lateral surface includes one or more surfaces defining the first recess.

Abstract: A semiconductor package includes an extendible molding member, a chip embedded in the molding member to have a warped shape, and connectors disposed in the molding member. First surfaces of the connectors are exposed at a surface of the molding member, and second surfaces of the connectors are coupled to the chip.

Abstract: Disclosed herein are a light emitting device package, a backlight unit, and a method of manufacturing a light emitting device package capable of being used for a display application or an illumination application.

Abstract: A semiconductor device includes a semiconductor substrate. The semiconductor substrate includes a plurality of first doping regions of a first doping structure arranged at a main surface of the semiconductor substrate and a plurality of second doping regions of the first doping structure arranged at the main surface of the semiconductor substrate. The first doping regions of the plurality of first doping regions of the first doping structure include dopants of a first conductivity type with different doping concentrations. Further, the second doping regions of the plurality of second doping regions of the first doping structure include dopants of a second conductivity type with different doping concentrations. At least one first doping region of the plurality of first doping regions of the first doping structure partly overlaps at least one second doping region of the plurality of second doping regions of the first doping structure causing an overlap region arranged at the main surface.

Abstract: A method for preparing a reference transistor test structure having a transistor with multiple terminals is provided. The method may include placing a set of bond pads at a first layer of the reference transistor test structure with each of the bond pads connecting to its corresponding terminal of the transistor, wherein the first layer of the reference transistor test structure is an uppermost metal layer. The method may further include placing a first protection device at a second layer of the reference transistor test structure and connecting the first protection device to at least one of the terminals of the transistor, wherein the second layer is a lowermost metal layer.

Abstract: A semiconductor wafer including first and second stacked bodies provided on separate parts of a substrate. The first stacked body includes a first insulating and a second insulating film being provided on the first portion, the second stacked body includes a plurality of third insulating films and a plurality of electrode films. The third insulating films and the electrode films are alternately stacked, and a shape of an end portion of the second stacked body on a side opposing to the first stacked body is a stepped pattern.

Abstract: A semiconductor memory device according to one embodiment, includes a stacked body including a plurality of electrode films stacked separated from each other along a first direction, a plurality of columnar structures extending in the first direction, piercing the stacked body, and including a semiconductor layer, a charge storage film provided between one of the columnar structures and the electrode films, and an insulating film dividing one of the electrode films disposed in an upper portion of the stacked body and not dividing other one of the electrode films disposed in a lower portion of the stacked body. A shortest distance between the columnar structures disposed on one side of the insulating film being shorter than a shortest distance between the columnar structures disposed with the insulating film interposed between the columnar structures.

Abstract: A semiconductor device includes a substrate layer, a redistribution layer (RDL) disposed over the substrate layer, a conductive bump disposed over the RDL, and a molding disposed over the RDL and surrounding the conductive bump, wherein the molding includes a protruded portion laterally protruded from a sidewall of the substrate layer and away from the conductive bump.

Abstract: A capped micromachined device has a movable micromachined structure in a first hermetic chamber and one or more interconnections in a second hermetic chamber that is hermetically isolated from the first hermetic chamber, and a barrier layer on its cap where the cap faces the first hermetic chamber, such that the first hermetic chamber is isolated from outgassing from the cap.

Abstract: A semiconductor device includes a substrate. The semiconductor device includes a gate electrode on the substrate. The semiconductor device includes a gate contact on the gate electrode. In some embodiments, a fin-shaped body protrudes from the substrate, and the gate electrode is on the fin-shaped body. Moreover, in some embodiments, the gate contact is partially in the gate electrode.

Abstract: A display device includes a first substrate arranged with a plurality of pixels on a first surface, the plurality of pixels having a display element including a transistor, and a first wiring connected to the transistor, a through electrode arranged in a first contact hole reaching the first wiring from a second surface facing the first surface of the first substrate, a second wiring connected with the through electrode, a first insulation film arranged covering the second wiring on the second surface of the first substrate, and a terminal connected with a second wiring via a second contact hole arranged in the first insulation film.

Abstract: A semiconductor device and a fabrication method thereof are provided. The semiconductor device includes a P type well region and an N type well region formed in a substrate, a gate insulating layer having a non-uniform thickness and formed on the P type well region and the N type well region, a gate electrode formed on the gate insulating layer, a P type well pick-up region formed in the P type well region, and a field relief oxide layer formed in the N type well region between the gate electrode and the drain region.

Abstract: A method for fabricating a semiconductor device comprises forming a sacrificial layer of a first semiconductor material on a substrate, a layer of a second semiconductor material on the sacrificial layer, and a layer of a third semiconductor material on the layer of the second semiconductor material. Portions of the layer of the deposited material are removed to form a first nanowire arranged on the sacrificial fin and a second nanowire arranged on the first nanowire. An oxidizing process is performed that forms a first layer of oxide material on exposed portions of the second nanowire and a second layer of oxide material on exposed portions of the sacrificial fin, the first layer of oxide material having a first thickness and the second layer of oxide material having a second thickness, where the first thickness is less than the second thickness.

Abstract: Semiconductor device fabrication methods are provided which include: providing a structure with at least one region and including a dielectric layer disposed over a substrate; forming a multilayer stack structure including a threshold-voltage adjusting layer over the dielectric layer, the multilayer stack structure including a first threshold-voltage adjusting layer in a first region of the at least one region, and a second threshold-voltage adjusting layer in a second region of the at least one region; and annealing the structure to define a varying threshold voltage of the at least one region, the annealing facilitating diffusion of at least one threshold voltage adjusting species from the first threshold-voltage adjusting layer and the second threshold-voltage adjusting layer into the dielectric layer, where a threshold voltage of the first region is independent of the threshold voltage of the second region.

Abstract: A plurality of pixels are arranged on the substrate. Each of the pixels is provided with an EL element which utilizes as a cathode a pixel electrode connected to a current control TFT. On a counter substrate, a light shielding film, a first color filter having a first color and a second color filter having a second color are provided. The second color is different from the first color.

Abstract: A Schottky diode is formed on a silicon support. A non-doped GaN layer overlies the silicon support. An AlGaN layer overlies the non-doped GaN layer. A first metallization forming an ohmic contact and a second metallization forming a Schottky contact are provided in and on the AlGaN layer. First vias extend from the first metallization towards the silicon support. Second vias extend from the second metallization towards an upper surface.

Abstract: An oxide semiconductor crystallization method may include depositing an In—Ga—Zn oxide over the substrate while heating a substrate to a temperature of 200 to 300° C., and heat-treating the deposited In—Ga—Zn oxide at a temperature of 200 to 350° C., thereby forming an oxide semiconductor layer crystallized throughout an entire thickness thereof.

Abstract: A semiconductor device according to embodiments described herein includes a p-type SiC layer, a gate electrode, and a gate insulating layer between the SiC layer and the gate electrode. The gate insulating layer includes a first layer, a second layer, a first region, and a second region. The second layer is between the first layer and the gate electrode and has a higher oxygen density than the first layer. The first region is provided across the first layer and the second layer, includes a first element from F, D, and H, and has a first concentration peak of the first element. The second region is provided in the first layer, includes a second element from Ge, B, Al, Ga, In, Be, Mg, Ca, Sr, Ba, Sc, Y, La, and lanthanoid, and has a second concentration peak of the second element and a third concentration peak of C.