Abstract: There are provided green-emitting quantum dots (QDs) including I-III-VI type ternary Cu—Ga—S core QDs and ZnS multishell wherein Cu:Ga is 1:10 to 1:1, and a fabricating method thereof. Integration of these QDs and red-emitting QDs into a blue LED leads to the fabrication of a white light-emitting device with high color rendering index. There are also provided blue-emitting QDs including I-III-VI type quaternary Zn—Cu—Ga—S or Cu—Ga—Al—S core QDs and ZnS multishell, and a fabricating method thereof. An electrically-driven blue light-emitting device with a QD emitting layer including these QDs interposed between a hole transport layer and an electron transport layer is fabricated.

Abstract: Conductive adhesive films can include a binding material having a first set of conductive particles therewithin. The binding material can be electrically non-conductive and can flow between and bond external electronic components during a bonding process. The first set of conductive particles can each have cores formed of a first material, such as polymer, and coatings surrounding the cores, the coatings formed of a second material that is electrically conductive, such as nickel. The binding material can also include a second set of smaller conductive particles formed of a third material that is electrically conductive, such as copper, which can have coatings formed of a fourth material that is electrically conductive, such as silver. The first set of conductive particles can each be sphere shaped, and the second set of conductive particles can each be flake shaped. The conductive particles can form electrical paths between the external electronic components.

Abstract: A capacitor includes a plurality of first electrode layers stacked in a first direction, a first conductor extending in the first direction through the plurality of first electrode layers, and a first insulating layer extending in the first direction along the first conductor and located between the first conductor and the plurality of first electrode layers. The capacitor includes a first capacitance provided between the first conductor and the plurality of first electrode layers.

Abstract: A sensor has an electronic chip and a sensor chip which are arranged within a functional volume which is at the most 4-5 mm long, a maximum 2-3 mm wide, and with a maximum height of 0.5-0.8 mm, thereby provide a potentially economical filter element having a compact sensor.

Abstract: Multigate devices and fabrication methods that mitigate the layout effects are described. In conventional processes to fabricate multigate semiconductor devices such as FinFET devices, long isolation cut masks may be used. This can lead to undesirable layout effects. To mitigate or eliminate the layout effect, fabrication methods are proposed in which the interlayer dielectric (ILD) layer remains intact at the gate cut location during the fabrication process.

Abstract: An integrated circuit (IC) structure includes a plurality of driver pins, each driver pin positioned at a driver pin level and oriented in a driver pin direction, and a plurality of layers of metal segment arrays. Each layer of metal segment arrays has a layer direction and includes two parallel metal segments oriented in the layer direction. The layer direction of a lowermost layer is perpendicular to the driver pin direction, the layer direction of each additional layer is perpendicular to the layer direction of a layer immediately below the additional layer, and each metal segment of a topmost layer is electrically connected to each driver pin of the plurality of driver pins.

Abstract: A method for fabricating a semiconductor device comprises forming a sacrificial layer of a first semiconductor material on a substrate, a layer of a second semiconductor material on the sacrificial layer, and a layer of a third semiconductor material on the layer of the second semiconductor material. Portions of the layer of the deposited material are removed to form a first nanowire arranged on the sacrificial fin and a second nanowire arranged on the first nanowire. An oxidizing process is performed that forms a first layer of oxide material on exposed portions of the second nanowire and a second layer of oxide material on exposed portions of the sacrificial fin, the first layer of oxide material having a first thickness and the second layer of oxide material having a second thickness, where the first thickness is less than the second thickness.

Abstract: Channel-to-substrate leakage in a FinFET device is prevented by inserting an insulating layer between the semiconducting channel and the substrate during fabrication of the device. Similarly, source/drain-to-substrate leakage in a FinFET device is prevented by isolating the source/drain regions from the substrate by inserting an insulating layer between the source/drain regions and the substrate. Forming such an insulating layer isolates the conduction path from the substrate both physically and electrically, thus preventing current leakage. In an array of semiconducting fins made up of a multi-layer stack, the bottom material is removed thus yielding a fin array that is suspended above the silicon surface. A resulting gap underneath the remaining top fin material is then filled with oxide to better support the fins and to isolate the array of fins from the substrate.

Abstract: A three-dimensional integrated circuit includes a first transistor, a word line, a first via, a second transistor, and a second via. The first transistor is on a first level and the second transistor is on a second level. The second level is different from the first level. The word line and the first via are coupled to the first transistor. The second via is coupled between the first transistor and the second transistor.

Abstract: A memory device includes at least one memory cell. The memory cell includes first and second transistors, and first and second capacitors. The first transistor is coupled to a source line. The second transistor is coupled to the first transistor and a bit line. The first capacitor is coupled to a word line and the second transistor. The second capacitor is coupled to the second transistor and an erase gate.

Abstract: A device comprises a semiconductor structure in a molding compound layer, a first polymer layer on the molding compound layer, a second polymer layer on the first polymer layer, a first interconnect structure having a first via portion in the first polymer layer and a first metal line portion in the second polymer layer, a third polymer layer on the second polymer layer, a fourth polymer layer on the third polymer layer and a second interconnect structure having a second via portion in the third polymer layer and a second metal line portion in the fourth polymer layer, wherein the second via portion is vertically aligned with the first via portion.

Abstract: A semiconductor device (100A) includes a substrate (101) and a thin film transistor (10) supported by the substrate. The thin film transistor includes a gate electrode (102), an oxide semiconductor layer (104), a gate insulating layer (103), a source electrode (105) and a drain electrode (106). The oxide semiconductor layer includes an upper semiconductor layer (104b) which is in contact with the source electrode and the drain electrode and which has a first energy gap, and a lower semiconductor layer (104a) which is provided under the upper semiconductor layer and which has a second energy gap that is smaller than the first energy gap. The source electrode and the drain electrode include a lower layer electrode (105a, 106a) which is in contact with the oxide semiconductor layer and which does not contain Cu, and a major layer electrode (105b, 106b) which is provided over the lower layer electrode and which contains Cu.

Abstract: A semiconductor device having a first die and a second die is provided. The first die of the device includes a first surface and a through-substrate via (TSV) extending at least substantially through the first die, the TSV having a portion extending past the first surface. The first die further includes a first substantially helical conductor disposed around the TSV. The second die of the device includes a second surface, an opening in the second surface in which the portion of the TSV is disposed, and a second substantially helical conductor disposed around the opening.

Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, the alternating stack containing a memory array region and a terrace region. Memory stack structures containing a memory film and a vertical semiconductor channel extend through the memory array region of the alternating stack. Support pillar structures extending through the terrace region of the alternating stack. The support pillar structures have different heights from each other.

Abstract: A display device includes a first substrate including a display region and a non-display region, the non-display region being positioned on an outside of the display region, a first dam in the non-display region of the substrate, the first dam including a first barrier and a first stopper, the first stopper being on the first barrier and having a concave groove formed thereon, and a first alignment layer covering the display region of the first substrate, at least a part of the first alignment layer extending to the non-display region and contacting a surface of the first stopper.

Abstract: A semiconductor device having a first die and a second die is provided. The first die of the device includes a first surface and a through-substrate via (TSV) extending at least substantially through the first die, the TSV having a portion extending past the first surface. The first die further includes a first substantially helical conductor disposed around the TSV. The second die of the device includes a second surface, an opening in the second surface in which the portion of the TSV is disposed, and a second substantially helical conductor disposed around the opening.

Abstract: A package includes a substrate, an Under-Bump Metallurgy (UBM) penetrating through the substrate, a solder region over and contacting the UBM, and an interconnect structure underlying the substrate. The interconnect structure is electrically coupled to the solder region through the UBM. A device die is underlying and bonded to the interconnect structure. The device die is electrically coupled to the solder region through the UBM and the interconnect structure. An encapsulating material encapsulates the device die therein.

Abstract: A semiconductor device (100A) includes: a substrate (1); a thin film transistor (101) whose active layer is an oxide semiconductor layer 5; at least one metal wiring layer including copper (7S, 7D); a metal oxide film including copper (8) arranged on an upper surface of the at least one metal wiring layer (7S, 7D); an insulating layer (11) covering at least one metal wiring layer with the metal oxide film (8) interposed therebetween; and a conductive layer (19) in direct contact with a portion of the at least one metal wiring layer, without the metal oxide film (8) interposed therebetween, in an opening formed in the insulating layer (11).

Abstract: A semiconductor device comprising a first transistor, a second insulating film, a conductive film, and a capacitor is provided. The first transistor comprises a first oxide semiconductor film, a gate insulating film over the first oxide semiconductor film, and a gate electrode over the gate insulating film. The second insulating film is provided over the gate electrode. The conductive film is electrically connected to the first oxide semiconductor film. The capacitor comprises a second oxide semiconductor film, the second insulating film over the second oxide semiconductor film, and the conductive film over the second insulating film. The first oxide semiconductor film comprises a first region and a second region. Each of a carrier density of the second region and a carrier density of the second oxide semiconductor film is higher than a carrier density of the first region.

Abstract: An array substrate and a manufacturing method thereof are disclosed. The array substrate includes: a glass substrate; a gate electrode; a first insulating layer; a semiconductor layer; a planarization layer mounted on the first insulating layer; a source electrode and a drain electrode; a pixel electrode layer mounted on the planarization layer and the drain electrode; a second insulating layer mounted on the planarization layer, the semiconductor layer, the source electrode and the drain electrode. The array substrate can prevent bubbles from forming at through holes and thereby increasing aperture ratio. The planarization layer further increases distances between the source electrode, the drain electrode and the gate electrode, which enhances antistatic ability.