Abstract: Provided is a semiconductor device having an RC-IGBT structure, the semiconductor device comprising an FWD (Free Wheel Diode) region and an IGBT (Insulated Gate Bipolar Transistor) region. Provided is a semiconductor device comprising: a semiconductor substrate; a transistor section formed on the semiconductor substrate; a diode section formed on the semiconductor substrate and including a lifetime killer at a front surface side of the semiconductor substrate; a gate runner provided between the transistor section and the diode section and electrically connected to a gate of the transistor section.

Abstract: A light-emitting device is provided. The light-emitting device includes a first electrode structure, a light-emitting layer disposed on the first electrode structure, a second electrode structure disposed on the light-emitting layer, and a plurality of nano-particles disposed within the light-emitting layer. Each of the nano-particles includes a metal core and a dielectric shell that surrounds the metal core to generate plasmon resonance.

Abstract: The present disclosure proposes a TFT array substrate and a method of forming the same. The TFT array substrate includes a substrate, a semi-conductor layer, a pixel electrode on the substrate so to be on the same layer as the semi-conductor layer, a gate insulating layer, a gate electrode, an ILD layer on the substrate so to cover the gate insulating layer, gate electrode and pixel electrode, a source electrode on the ILD layer and connected to the semi-conductor layer, and a drain electrode on the ILD layer and connected to the semi-conductor layer and pixel electrode. The TFT array substrate can prevent etching of the metal oxide by an etching solution. The TFT array substrate having a top-gate structure, including with a traditional TFT with a top-gate structure, can skip the use of photomask at two occasions during the production process, thus lowers the production cost.

Abstract: A radial solder ball pattern is described for a printed circuit board and for a chip to be attached to the printed circuit board is described. In one example, the pattern comprises a central power connector area having a plurality of power connectors to provide power to an attached chip, a signal area having a plurality of signal connectors to communicate signals to the attached chip, an edge area surrounding the signal area and the central power connector area, and a plurality of traces each coupled to a signal connector, the traces extending from the respective coupled signal connector away from the central power connector to connect to an external component, wherein the signal connectors are placed in rows, the rows having a greater separation near the edge area than near the central area.

Abstract: A semiconductor package is provided. The semiconductor package includes a carrier substrate having opposite first surface and second surface, and a chip stack disposed on the first surface of the carrier substrate. The chip stack includes a first semiconductor die, a second semiconductor die, and an interposer between the first semiconductor die and the second semiconductor die. The interposer transmits signals between the first semiconductor die and the second semiconductor die.

Abstract: Semiconductor devices, methods of manufacturing thereof, and image sensor devices are disclosed. In some embodiments, a semiconductor device comprises a semiconductor chip comprising an array region, a periphery region, and a through-via disposed therein. The semiconductor device comprises a guard structure disposed in the semiconductor chip between the array region and the through-via or between the through-via and a portion of the periphery region.

Abstract: To restrict alloy formation between a hydrogen-absorbing layer of titanium or the like and an electrode of aluminum or the like, provided is a semiconductor device. The semiconductor device may include a semiconductor substrate. The semiconductor device may include a first layer that is formed above the semiconductor substrate. The first layer may contain a hydrogen-absorbing first metal. The semiconductor device may include a second layer that is formed above the first layer. The second layer may contain a second metal differing from the first metal. The semiconductor device may include an Si-containing layer that is formed between the first layer and the second layer and contains silicon. The second layer may further include silicon. The Si-containing layer may have a higher silicon concentration than the second layer. The second metal may be aluminum. The first metal may be titanium.

Abstract: Provided is a flexible display device including a flexible display panel having a substrate and an organic electroluminescent member disposed on the substrate, a window member disposed on the flexible display panel, and a protection member disposed under the flexible display panel, wherein the protection member includes a metal layer disposed under the substrate, a cushion layer disposed under the metal layer, and a planarization layer and disposed between the metal layer and the cushion layer.

Abstract: A semiconductor package includes: a first semiconductor chip in which a through-electrode is provided; a second semiconductor chip connected to a top surface of the first semiconductor chip; a first connection bump attached to a bottom surface of the first semiconductor chip and including a first pillar structure and a first solder layer; and a second connection bump located between the first semiconductor chip and the second semiconductor chip, configured to electrically connect the first semiconductor chip and the second semiconductor chip, and including a second pillar structure and a second solder layer.

Abstract: The present invention discloses an OLED display panel, comprising a substrate; a semitransparent cathode, formed on the substrate; an emission layer, formed at one side of the semitransparent cathode away from the substrate; a transparent anode, formed at one side of the emission layer away from the semitransparent cathode; and a photochromic layer, being formed at one side of the transparent anode away from the emission layer, and the photochromic layer comprises photochromic material which changes from transparent to opaque under excitation of light, and the light emitted by the emission layer comprises a wavelength employed to excite the photochromic material. The OLED display panel of the present invention has the longer micro cavity total optical distance. The present invention further discloses a manufacture method of an OLED display panel.

Abstract: A system-in-package (SiP) includes a RDL structure having a first side and a second side opposite to the first side; a first semiconductor die mounted on the first side of the RDL structure, wherein the first semiconductor die has an active surface that is in direct contact with the RDL structure; a plurality of conductive fingers on the first side of the RDL structure around the first semiconductor die; a second semiconductor die stacked directly on the first semiconductor die, wherein the second semiconductor die is electrically connected to the plurality of conductive fingers through a plurality of bond wires; and a mold cap encapsulating the first semiconductor die, the conductive fingers, the second semiconductor die, and the first side of the RDL structure.

Abstract: A light-emitting element includes a light transmissive substrate, a semiconductor layered body, and first and second light reflecting members. The semiconductor layered body is formed on a first main surface of the light transmissive substrate. The first light reflecting member covers a first lateral surface, a second lateral surface, a fourth lateral surface, and a second main surface of the light transmissive substrate. The second light reflecting member covers a surface of the semiconductor layered body that is opposite from a surface on which the light transmissive substrate is disposed. A cross-sectional plane of the light transmissive substrate parallel to the first main surface has a concave figure that includes a recess, and the third lateral surface includes one or more surfaces defining the recess.

Abstract: An electrical interconnect assembly for use in an integrated circuit package includes a mounting substrate having a thickness defined between a first surface and a second surface thereof and at least one electrically conductive pad formed on the first surface of the mounting substrate. A metallization layer coats a surface of the at least one electrically conductive pad and is electrically coupled thereto. The metallization layer also coats portion of the first surface of the mounting substrate and extends through at least one via formed through the thickness of the mounting substrate. A method of manufacturing an electrical interconnect assembly includes forming at least one top side contact pad on a top surface of a mounting substrate and depositing a metallization layer on the top side contact pad(s), on an exposed portion of the top surface, and into via(s) formed through a thickness of the mounting substrate.

Abstract: The present disclosure relates to an integrated circuit, and an associated method of formation. In some embodiments, the integrated circuit comprises a deep trench grid disposed at a back side of a substrate. A passivation layer lines the deep trench grid within the substrate. The passivation layer includes a first high-k dielectric layer and a second high-k dielectric layer disposed over the first high-k dielectric layer. A first dielectric layer is disposed over the passivation layer, lining the deep trench grid and extending over an upper surface of the substrate. A second dielectric layer is disposed over the first dielectric layer and enclosing remaining spaces of the deep trench grid to form air-gaps at lower portions of the deep trench grid. The air-gaps are sealed by the first dielectric layer or the second dielectric layer below the upper surface of the substrate.

Abstract: A method of manufacturing an integrated circuit including forming trenches into the surface of a crystalline wafer and the trenches extending along a <100> lattice direction is disclosed. Such wafer can experience less deformation due to less stress induced when the trenches are filled using a spin-on dielectric material. Thus, the overlay issue caused by wafer shape change is resolved.

Abstract: A method of dies singulation includes providing a carrier, disposing a plurality of dies over a surface of the carrier according to a plurality of scribe lines comprising a plurality of continuous lines along a first direction and a plurality of discontinuous lines along a second direction, cutting the carrier according to the plurality of continuous lines along the first direction, and cutting the carrier according to the plurality of discontinuous lines along the second direction.

Abstract: A change in electrical characteristics is suppressed and reliability in a semiconductor device using a transistor including an oxide semiconductor is improved. One feature resides in forming an oxide semiconductor film over an oxygen-introduced insulating film, and then forming the source and drain electrodes with an antioxidant film thereunder. Here, in the antioxidant film, the width of a region overlapping with the source and drain electrodes is longer than the width of a region not overlapping with them. The transistor formed as such has less defects in the channel region, which will improve reliability of the semiconductor device.

Abstract: An on-chip metal-insulator-metal (MIM) capacitor with enhanced capacitance is provided by forming the MIM capacitor along sidewall surfaces and a bottom surface of each trench of a plurality of trenches formed in a back-end-of-the-line (BEOL) metallization stack to increase a surface area of the MIM capacitor.

Abstract: A method for fabricating a semiconductor memory device is provided. The method includes: etching a first region of the semiconductor memory device to expose a first capping layer; forming a second capping layer on the first capping layer; etching a portion of the first capping layer and a portion of the second capping layer to form a first trench reaching a first metal line; and forming a second metal line in the first trench to contact the first metal line.

Abstract: Disclosed is a semiconductor device suppressed in decrease of reliability. The semiconductor device comprises an electrode pad portion (2) formed on the upper surface of a semiconductor substrate (1), a passivation layer (3) so formed on the upper surface of the semiconductor substrate (1) as to overlap a part of the electrode pad portion (2) and having a first opening portion (3a) where the upper surface of the electrode pad portion (2) is exposed, a barrier metal layer (5) formed on the electrode pad portion (2), and a solder bump (6) formed on the barrier metal layer (5). The barrier metal layer (5) is formed such that an outer peripheral end (5b) lies within the first opening portion (3a) of the passivation layer (3) when viewed in plan.