Abstract: A microelectronic package includes an interposer with through-silicon vias that is formed from a semiconductor substrate and one or more semiconductor dies coupled to the interposer. A first signal redistribution layer formed on the first side of the interposer electrically couples the one or more semiconductor dies to the through-silicon vias. A second redistribution layer is formed on a second side of the interposer, and is electrically coupled to the through-silicon vias. In some embodiments, a mold compound is connected to an edge surface of the interposer and is configured to stiffen the microelectronic package.

Abstract: A display device includes a first substrate arranged with a plurality of pixels on a first surface, the plurality of pixels having a display element including a transistor, and a first wiring connected to the transistor, a through electrode arranged in a first contact hole reaching the first wiring from a second surface facing the first surface of the first substrate, a second wiring connected with the through electrode, a first insulation film arranged covering the second wiring on the second surface of the first substrate, and a terminal connected with a second wiring via a second contact hole arranged in the first insulation film.

Abstract: A semiconductor device including a p-type SiC layer, a gate electrode, and a gate insulating layer therebetween, the gate insulating layer including a first layer, a second layer provided between the first layer and the gate electrode and having a higher oxygen density than the first layer, a first and second regions provided in the second layer, the first region including a first element (at least one of Ta, Nb and V) having a first concentration peak, and the second region including a second element (at least one of Ge, B, Al, Ga, In, Be, Mg, Ca, Sr, Ba , La, and lanthanoid) having a second concentration peak of the second element and a third concentration peak of C, a distance between the second concentration peak and the third concentration peak being shorter than a distance between the first concentration peak and the third concentration peak.

Abstract: A semiconductor device includes a semiconductor substrate, an insulating film formed above the semiconductor substrate, a wiring having copper as a main component and formed above the insulating film, and a barrier metal film having a higher modulus of rigidity than copper and interposed between the insulating film and the wiring. The barrier metal film may have a lower thermal expansion coefficient than copper.

Abstract: A circuit substrate includes: a base material; and a capacitor layer. The capacitor layer includes a first metal layer that is provided on the base material, a dielectric layer that is provided on the first metal layer, and a second metal layer that is provided on the dielectric layer. The first metal layer includes a first electrode region which is provided on the base material and is exposed from the dielectric layer and to which a first terminal of a capacitor element for supplying current to a circuit part through the capacitor layer is connected. The second metal layer includes a second electrode region in which the second metal layer is exposed and to which a second terminal of the capacitor element is connected.

Abstract: A semiconductor structure includes a semiconductor substrate, a pad, a circuit board, a first bump, and a second bump. The pad is disposed on a top surface of the semiconductor substrate. The circuit board includes a contact area corresponding to the pad on the top surface of the semiconductor substrate. The first bump is between the pad on the top surface of the semiconductor substrate and the contact area, wherein the contact area includes a non-metallic surface. The second bump is adjacent the first bump, wherein a first central width of the first bump is larger than a second central width of the second bump.

Abstract: A semiconductor pressure sensor device in which the shape or the structure of a connector portion can be easily changed and which has high waterproof performance. A terminal housing and a second case are engaged with each other via an engagement structure. The terminal housing and a first case are fitted with each other via a fitting structure. Thus, the first case and the second case are fixed to each other via the terminal housing. The first case is fitted in the second case. Then, the terminal housing is fitted with the first case, and the terminal housing is engaged with the second case substantially at the same time. Through such simple process, an opening portion of the first case is covered and a connector portion configured to enable external terminals to be connected to ends, located on one side, of a plurality of lead terminals is formed.

Abstract: An integrated circuit chip includes a semiconductor substrate having thereon a plurality of inter-metal dielectric (IMD) layers and a plurality of first conductive layers embedded in respective said plurality of IMD layers, wherein said first conductive layers comprise copper; a first insulating layer overlying said plurality of IMD layers and said plurality of first conductive layers; at least a first wiring line in a second conductive layer overlying said first insulating layer, for distributing power signal or ground signal, wherein said second conductive layer comprise aluminum; and at least a second wiring line in a third conductive layer overlying said second conductive layer, for distributing power signal or ground signal.

Abstract: A highly reliable light-emitting device is provided. Damage to an element due to externally applied physical power is suppressed. Alternatively, in a process of pressure-bonding of an FPC, damage to a resin and a wiring which are in contact with a flexible substrate due to heat is suppressed. A neutral plane at which stress-strain is not generated when a flexible light-emitting device including an organic EL element is deformed, is positioned in the vicinity of a transistor and the organic EL element. Alternatively, the hardness of the outermost surface of a light-emitting device is high. Alternatively, a substrate having a coefficient of thermal expansion of 10 ppm/K or lower is used as a substrate that overlaps with a terminal portion connected to an FPC.

Abstract: Multigate devices and fabrication methods that mitigate the layout effects are described. In conventional processes to fabricate multigate semiconductor devices such as FinFET devices, long isolation cut masks may be used. This can lead to undesirable layout effects. To mitigate or eliminate the layout effect, fabrication methods are proposed in which the interlayer dielectric (ILD) layer remains intact at the gate cut location during the fabrication process.

Abstract: An image sensor includes a substrate including an active region defined by a device isolation layer, a photoelectric conversion layer in the substrate, a floating diffusion region in the substrate at an edge of the active region, and a transfer gate on the active region. The transfer gate is in contact with a portion of the device isolation layer adjacent the active region.

Abstract: An optoelectronic semiconductor component includes an optoelectronic semiconductor chip having a top area at a top side, a bottom area at an underside, and side areas connecting the top area and the bottom area; electrical contact locations at the top area or at the bottom area of the optoelectronic semiconductor chip; and an electrically insulating shaped body, wherein the optoelectronic semiconductor chip is a flip-chip having the electrical contract locations only at one side, either the underside or the top side, the shaped body surrounds the optoelectronic semiconductor chip at its side areas, and the shaped body is free of a via that electrically connects the optoelectronic semiconductor chip.

Abstract: A semiconductor package includes a molding member, a chip embedded in the molding member to have a warped shape, and connectors disposed in the molding member. The molding member includes an extendible material which includes a first part having a warped shape, a second part extending from one end of the first part to be flat, and a third part extending from the other end of the first part to be flat, where first surfaces of the connectors are exposed at a surface of the molding member and second surfaces of the connectors are coupled to the chip.

Abstract: A highly reliable semiconductor device the yield of which can be prevented from decreasing due to electrostatic discharge damage is provided. A semiconductor device is provided which includes a gate electrode layer, a gate insulating layer over the gate electrode layer, an oxide insulating layer over the gate insulating layer, an oxide semiconductor layer being above and in contact with the oxide insulating layer and overlapping with the gate electrode layer, and a source electrode layer and a drain electrode layer electrically connected to the oxide semiconductor layer. The gate insulating layer includes a silicon film containing nitrogen. The oxide insulating layer contains one or more metal elements selected from the constituent elements of the oxide semiconductor layer. The thickness of the gate insulating layer is larger than that of the oxide insulating layer.

Abstract: A display device includes first to fifth insulating films, first to third conductive films, semiconductor film, a planarization layer, an organic resin film, a pixel electrode, an opposing electrode and a light-emitting member. The first insulating film includes nitrogen. The second and third insulating films include oxygen. The fifth insulating film is an inorganic insulating film. The fourth insulating film, the fifth insulating film, the planarization layer and the organic resin film include first to fourth opening, respectively. An edge portion of the third opening and an edge portion of the fourth opening are rounded. Part of the third conductive film and part of the planarization layer are located in the second opening. Part of the pixel electrode and part of the organic resin film are located in the third opening. Part of the light-emitting member and part of the opposing electrode are located in the fourth opening.

Abstract: A method for manufacturing a semiconductor device is discussed. The method includes forming a gate electrode on a substrate, forming a gate insulating film over the substrate, depositing an In—Ga—Zn oxide over the gate insulating film while heating the substrate to a temperature of 200 to 300° C., an atomic percent ratio of Zn in the In—Ga—Zn oxide as-deposited being higher than that of In or Ga, heat-treating the deposited In—Ga—Zn oxide at a temperature of 200 to 350° C., thereby forming an active layer crystallized throughout an entire thickness of the active layer, and forming a source electrode and a drain electrode.

Abstract: A transistor with stable electric characteristics is provided. An aluminum oxide film containing boron is formed in order to prevent hydrogen from diffusing into an oxide semiconductor film.

Abstract: A method includes attaching a semiconductor structure on a carrier, depositing a molding compound layer over the carrier, wherein the semiconductor structure is embedded in the molding compound layer, exposing a first photo-sensitive material layer and a second photo-sensitive material layer to light, developing the first photo-sensitive material layer and the second photo-sensitive material layer to form an opening having a first portion in the first photo-sensitive material layer and a second portion in the second photo-sensitive material layer, wherein a width of the second portion is greater than a width of the first portion, filling the opening with a conductive material to form a via in the first photo-sensitive material layer and a redistribution layer in the second photo-sensitive material layer and forming a bump over the redistribution layer.

Abstract: Methods of forming semiconductor device structures include forming trenches in an array region and in a buried digit line end region, forming a metal material in the trenches, filling the trenches with a mask material, removing mask material in the trenches to expose a portion of the metal material, and removing the exposed portion of the metal material. A plurality of conductive contacts is formed in direct contact with the metal material in the buried digit line end region. Methods of forming a buried digit line contact include forming conductive contacts physically contacting metal material in trenches in a buried digit line end region. Vertical memory devices and apparatuses include metallic connections disposed between a buried digit line and a conductive contact in a buried digit line end region.

Abstract: Aspects of the present disclosure are directed to circuitry operable with enhanced capacitance and mitigation of avalanche breakdown. As may be implemented in accordance with one or more embodiments, an apparatus and/or method involves respective transistors of a cascode circuit, one of which controls the other in an off state by applying a voltage to a gate thereof. A plurality of doped regions are separated by trenches, with the conductive trenches being configured and arranged with the doped regions to provide capacitance across the source and the drain of the second transistor, and restricting voltage at one of the source and the drain of the second transistor, therein mitigating avalanche breakdown of the second transistor.