Abstract: Embodiments include Multiple Gate Field-Effect Transistors (MuGFETs) and methods of forming them. In an embodiment, a structure includes a substrate, a fin, masking dielectric layer portions, and a raised epitaxial lightly doped source/drain (LDD) region. The substrate includes the fin. The masking dielectric layer portions are along sidewalls of the fin. An upper portion of the fin protrudes from the masking dielectric layer portions. A first spacer is along a sidewall of a gate structure over a channel region of the fin. A second spacer is along the first spacer. The raised epitaxial LDD region is on the upper portion of the fin, and the raised epitaxial LDD region adjoins a sidewall of the first spacer and is disposed under the second spacer. The raised epitaxial LDD region extends from the upper portion of the fin in at least two laterally opposed directions and a vertical direction.

Abstract: An integrated circuit (IC) structure includes a plurality of driver pins at a driver pin level and oriented in a driver pin direction. Each layer of a plurality of layers of metal segment arrays includes two parallel metal segments oriented in a layer direction. The layer direction of a lowermost layer is perpendicular to the driver pin direction, and the layer direction of each additional layer is perpendicular to the layer direction of a layer immediately below the additional layer. The IC structure also includes a plurality of via arrays, each via array including two vias positioned at locations where one or more metal segments of a corresponding overlying layer overlap one or more of the two metal segments of a layer immediately below the via array or the plurality of driver pins.

Abstract: An image sensor includes a semiconductor substrate, a first pair of photoelectric conversion regions in a first pixel region of the substrate and a first isolation structure between the photoelectric conversion regions of the first pair of photoelectric conversion regions. The sensor further includes a second pair of photoelectric conversion regions in a second pixel region of the substrate adjacent the first pixel region and a second isolation structure between the photoelectric conversion regions of the second pair of photoelectric conversion regions and having different optical properties than the first isolation structure. First and second different color filters (e.g., green and red) may be disposed on respective ones of the first and second pixel regions.

Abstract: Integrated circuits, nonvolatile memory (NVM) structures, and methods for fabricating integrated circuits with NVM structures are provided. An exemplary integrated circuit includes a substrate and a dual-bit NVM structure overlying the substrate. The dual-bit NVM structure includes primary, first adjacent and second adjacent fin structures laterally extending in parallel over the substrate. The primary fin structure includes source, channel and drain regions. Each adjacent fin structure includes a program/erase gate. The dual-bit NVM structure further includes a first floating gate located between the channel region of the primary fin structure and the first adjacent fin structure and a second floating gate located between the channel region of the primary fin structure and the second adjacent fin structure. Also, the dual-bit NVM structure includes a control gate adjacent the primary fin structure.

Abstract: Semiconductor devices having MIM capacitor structures are provided, as well as methods for fabricating semiconductor devices having MIM capacitor structures. For example, a semiconductor device includes a first capacitor electrode formed on a substrate, a capacitor insulating layer formed on the first capacitor electrode, and a second capacitor electrode. The second capacitor electrode comprises a layer of metallic material that is formed by application of a surface treatment to a surface of the capacitor insulating layer to convert the surface of the capacitor insulating layer to the layer of metallic material. As an example, the capacitor insulating layer comprises Ta3N5 insulating material, and the second capacitor electrode comprises TaN metallic material.

Abstract: Channel-to-substrate leakage in a FinFET device is prevented by inserting an insulating layer between the semiconducting channel and the substrate during fabrication of the device. Similarly, source/drain-to-substrate leakage in a FinFET device is prevented by isolating the source/drain regions from the substrate by inserting an insulating layer between the source/drain regions and the substrate. Forming such an insulating layer isolates the conduction path from the substrate both physically and electrically, thus preventing current leakage. In an array of semiconducting fins made up of a multi-layer stack, the bottom material is removed thus yielding a fin array that is suspended above the silicon surface. A resulting gap underneath the remaining top fin material is then filled with oxide to better support the fins and to isolate the array of fins from the substrate.

Abstract: Vertical transistor devices are described. For example, in one embodiment, a vertical transistor device includes an epitaxial source semiconductor region disposed on a substrate, an epitaxial channel semiconductor region disposed on the source semiconductor region, an epitaxial drain semiconductor region disposed on the channel semiconductor region, and a gate electrode region surrounding sidewalls of the semiconductor channel region. A composition of at least one of the semiconductor regions varies along a longitudinal axis that is perpendicular with respect to a surface of the substrate.

Abstract: A semiconductor device includes a GaN FET with an overvoltage clamping component electrically coupled to a drain node of the GaN FET and coupled in series to a voltage dropping component. The voltage dropping component is electrically coupled to a terminal which provides an off-state bias for the GaN FET. The overvoltage clamping component conducts insignificant current when a voltage at the drain node of the GaN FET is less than the breakdown voltage of the GaN FET and conducts significant current when the voltage rises above a safe voltage limit. The voltage dropping component is configured to provide a voltage drop which increases as current from the overvoltage clamping component increases. The semiconductor device is configured to turn on the GaN FET when the voltage drop across the voltage dropping component reaches a threshold value.

Abstract: A method for forming a hybrid semiconductor device includes growing a stack of layers on a semiconductor substrate. The stack of layers includes a bottom layer in contact with the substrate, a middle layer on the bottom layer and a top layer on the middle layer. First and second transistors are formed on the top layer. A protective dielectric is deposited over the first and second transistors. A trench is formed adjacent to the first transistors to expose the middle layer. The middle layer is removed from below the first transistors to form a cavity. A dielectric material is deposited in the cavity to provide a transistor on insulator structure for the first transistors and a bulk substrate structure for the second transistors.

Abstract: A memory device includes a plurality of gate electrode layers, an interlayer insulating layer, a plurality of contact plugs, and at least one contact insulating layer. The gate electrode layers extend in a first direction and have different lengths to form a step structure. The interlayer insulating layer is on the gate electrode layers. The contact plugs are connected to the gate electrode layers through the interlayer insulating layer. The at least one contact insulating layer is within the interlayer insulating layer and surrounds one or more of the contact plugs. The at least one contact insulating layer extends in the first direction.

Abstract: A method of making a display device includes, providing a substrate having a display area and a pad area in a periphery of the display area, the display area including a plurality of pixel regions; forming a thin film transistor having a channel layer on the substrate; arranging a gate link line and a first common voltage line to cross each other, and having a first insulation film be interposed therebetween; arranging a second common voltage line and a data link line to cross each other, and having second insulation film be interposed therebetween; disposing a first pattern on the first insulation film; and disposing a second pattern on the second insulation film, wherein the channel layer, the first pattern and the second pattern are formed of the same material.

Abstract: There is provided a structure and a method of manufacturing a semiconductor package. The method includes disposing a first semiconductor device and through mold ball connectors (TMBCs) on a first surface of an interconnection structure layer, recessing a molding layer on the first surface of the interconnection structure layer to expose a portion of each of the TMBCs, attaching outer connectors to the exposed portions of the TMBCs, and mounting a second semiconductor device on a second surface of the interconnection structure layer opposite to the molding layer.

Abstract: A representative device includes a patterned opening through a layer at a surface of a device die. A liner is disposed on sidewalls of the opening and the device die is patterned to extend the opening further into the device die. After patterning, the liner is removed. A conductive pad is formed in the device die by filling the opening with a conductive material.

Abstract: An optoelectronic component and a method for manufacturing an optoelectronic component are provided. In an embodiment, the optoelectronic component includes a layer sequence having an active layer configured to emit electromagnetic primary radiation, a converter lamina disposed in a beam path of the electromagnetic primary radiation and a bonding layer disposed between the layer sequence and the converter lamina, wherein the bonding layer comprises an inorganic-organic hybrid material having Si—O—Al bonds and/or Si—O—Zr bonds.

Abstract: A display device includes a first substrate including a display region and a non-display region, the non-display region being positioned on an outside of the display region, a first dam in the non-display region of the substrate, the first dam including a first barrier and a first stopper, the first stopper being on the first barrier and having a concave groove formed thereon, and a first alignment layer covering the display region of the first substrate, at least a part of the first alignment layer extending to the non-display region and contacting a surface of the first stopper. A method of fabricating the display device includes preparing the first substrate, forming the first dam in the non-display region of the first substrate, and forming the first alignment layer covering the display region of the first substrate extending to the non-display region and contacting a surface of the first stopper.

Abstract: A semiconductor device comprising a first transistor, a second insulating film, a conductive film, and a capacitor is provided. The first transistor comprises a first oxide semiconductor film, a gate insulating film over the first oxide semiconductor film, and a gate electrode over the gate insulating film. The second insulating film is provided over the gate electrode. The conductive film is electrically connected to the first oxide semiconductor film. The capacitor comprises a second oxide semiconductor film, the second insulating film over the second oxide semiconductor film, and the conductive film over the second insulating film. The first oxide semiconductor film comprises a first region and a second region. Each of a carrier density of the second region and a carrier density of the second oxide semiconductor film is higher than a carrier density of the first region.

Abstract: A semiconductor device with a metal gate is disclosed. An exemplary semiconductor device with a metal gate includes a semiconductor substrate, source and drain features on the semiconductor substrate, a gate stack over the semiconductor substrate and disposed between the source and drain features. The gate stack includes a HK dielectric layer formed over the semiconductor substrate, a plurality of barrier layers of a metal compound formed on top of the HK dielectric layer, wherein each of the barrier layers has a different chemical composition; and a stack of metals gate layers deposited over the plurality of barrier layers.

Abstract: A semiconductor device includes: opposed first and second metal plates; a plurality of semiconductor elements each interposed between the first metal plate and the second metal plate; a metal block interposed between the first metal plate and each of the semiconductor elements; a solder member interposed between the first metal plate and the metal block and connecting the first metal plate to the metal block; and a resin molding sealing the semiconductor elements and the metal block. A face of the first metal plate, which is on an opposite side of a face of the first metal plate to which the metal block is connected via the solder member, is exposed from the resin molding. The first metal plate has a groove formed along an outer periphery of a region in which the solder member is provided, the groove collectively surrounding the solder member.

Abstract: A highly reliable semiconductor device the yield of which can be prevented from decreasing due to electrostatic discharge damage is provided. A semiconductor device is provided which includes a gate electrode layer, a first gate insulating layer over the gate electrode layer, a second gate insulating layer being over the first gate insulating layer and having a smaller thickness than the first gate insulating layer, an oxide semiconductor layer over the second gate insulating layer, and a source electrode layer and a drain electrode layer electrically connected to the oxide semiconductor layer. The first gate insulating layer contains nitrogen and has a spin density of 1×1017 spins/cm3 or less corresponding to a signal that appears at a g-factor of 2.003 in electron spin resonance spectroscopy. The second gate insulating layer contains nitrogen and has a lower hydrogen concentration than the first gate insulating layer.

Abstract: A semiconductor device includes a substrate, a circuit layer formed on a first surface of the substrate and including a via pad and an interlayer insulating layer covering the via pad, a via structure configured to fully pass through the substrate, partially pass through the interlayer insulating layer and be in contact with the via pad, a via isolation insulating layer configured to pass through the substrate and be spaced apart from outer side surfaces of the via structure in a horizontal direction and a pad structure buried in the substrate and exposed on a second surface of the substrate opposite the first surface of the substrate.