Abstract: A TFT device is manufactured starting from a substrate with mutually insulated elongated strips of semi-conductor material. A stack of layers over the strips on the substrate, the stack comprising a gate electrode layer. A multi-level resist layer is provided over the gate electrode layer. The multi-level resist layer defines gate and source drain regions, the channel running in parallel with the direction of the strips. Gate portions in the resist layer cross source drain regions in the resist layer, overreaching the source drain regions on either side at least by a distance corresponding to a pitch of the strips.

Abstract: A semiconductor device structure comprising: a layer of compound semiconductor material; and a layer of polycrystalline CVD diamond material, wherein the layer of polycrystalline CVD diamond material is bonded to the layer of compound semiconductor material via a layer of nano-crystalline diamond which is directly bonded to the layer of compound semiconductor material, the layer of nano-crystalline diamond having a thickness in a range 5 to 50 nm and configured such that an effective thermal boundary resistance (TBReff) as measured by transient thermoreflectance at an interface between the layer of compound semiconductor material and the layer of polycrystalline CVD diamond material is no more than 50 m2K/GW.

Abstract: An integrated circuit (IC) structure including an interconnect structure is disclosed. The interconnect structure may include a first etch stop layer (ESL) positioned between an initial via layer and a first metal layer of the interconnect structure. The ESL may be positioned adjacent to and surround a metal wire in the first metal layer. A method of forming an interconnect structure is also disclosed. The method may include forming an opening in a first dielectric layer above a substrate; forming a sacrificial semiconductor material in the opening; forming an ESL on the first dielectric layer and sacrificial semiconductor material; forming a second dielectric layer on the ESL; forming an opening in the second dielectric layer to expose a portion of the ESL; removing the exposed portion of the ESL; removing the sacrificial semiconductor material; and forming a conductive material in the openings to form an interconnect structure.

Abstract: A semiconductor device with a metal gate is disclosed. An exemplary semiconductor device with a metal gate includes a semiconductor substrate, source and drain features on the semiconductor substrate, a gate stack over the semiconductor substrate and disposed between the source and drain features. The gate stack includes a HK dielectric layer formed over the semiconductor substrate, a plurality of barrier layers of a metal compound formed on top of the HK dielectric layer, wherein each of the barrier layers has a different chemical composition; and a stack of metals gate layers deposited over the plurality of barrier layers.

Abstract: A semiconductor memory device is provided, and which includes a substrate, plural gates, plural plugs, a capacitor structure and a conducting cap layer. The gates are disposed within the substrate, and the plugs are disposed on the substrate, with each plug electrically connected to two sides of each gate on the substrate. The capacitor structure is disposed on the substrate, and the capacitor structure includes plural capacitors, with each capacitor electrically connected to the plugs respectively. The conducting cap layer covers the top surface and sidewalls of the capacitor structure. Also, the semiconductor memory device further includes an adhesion layer and an insulating layer. The adhesion layer covers the conducting cap layer and the capacitor structure, and the insulating layer covers the adhesion layer.

Abstract: An integrated circuit for a flash memory device with enlarged spacing between select and memory gate structures is provided. The enlarged spacing is obtained by forming corner recesses at the select gate structure so that a top surface with a reduced dimension of the select gate structure is obtained. In one example, a semiconductor substrate having memory cell devices formed thereon, the memory cell devices includes a semiconductor substrate having memory cell devices formed thereon, the memory cell devices includes a plurality of select gate structures and a plurality of memory gate structures formed adjacent to the plurality of select gate structures, wherein at least one of the plurality of select gate structures have a corner recess formed below a top surface of the at least one of the plurality of select gate structures.

Abstract: An electronic device has a first surface, a second surface opposite to the first surface, and sidewalls located between and adjoining the first and second surfaces. The electronic device includes contact pads on the first surface. The contact pads extend from the first surface to adjoining sidewalls, and abut the sidewalls.

Abstract: A semiconductor device structure includes a layer of single crystal compound semiconductor material; and a layer of polycrystalline CVD diamond material. The layer of polycrystalline CVD diamond material is bonded to the layer of single crystal compound semiconductor material via a bonding layer having a thickness of less than 25 nm and a thickness variation of no more than 15 nm. The effective thermal boundary resistance as measured by transient thermoreflectance at an interface between the layer of single crystal compound semiconductor material and the layer of polycrystalline CVD diamond material is less than 25 m2K/GW with a variation of no more than 12 m2K/GW as measured across the semiconductor device structure. The layer of single crystal compound semiconductor material has one or both of the following characteristics: a charge mobility of at least 1200 cm2V?1s?1; and a sheet resistance of no more than 700 ?/square.

Abstract: A method comprising bonding a first substrate to a second substrate. The first substrate includes a layer of one or more pairs of reactive material. The method comprising triggering a reaction between the one or more pairs of reactive material and fragmenting the second substrate.

Abstract: A power semiconductor module includes one or more power semiconductor dies attached to a first main face of a substrate, a plastic housing attached to the substrate, which together with the substrate encloses the one or more power semiconductor dies, a plurality of power terminals attached to the first main face of the substrate at a first end, and extending through the plastic housing at a second end to provide a point of external electrical connection for the one or more power semiconductor dies, a potting compound embedding the one or more power semiconductor dies, the first main face of the substrate and at least part of the first end of the plurality of power terminals, and an insulative coating applied only to parts of the plurality of power terminals disposed inside the plastic housing and in contact with just air. A corresponding method of manufacture also is provided.

Abstract: A silicon carbide (SiC) structure and a method of forming the SiC structure are disclosed. The SiC structure includes an SiC substrate and a film provided on the SiC substrate. The SiC substrate contains both of a hexagonal close packed (hcp) structure and a face centered cubic (fcc) structure, and has only one of the hcp surface and the fcc surface, where the hcp surface includes atoms in the topmost layer whose rows overlap with rows of atoms in the third layer, while, the fcc surface includes atoms in the topmost layer whose rows are different from rows of atoms in the third layer.

Abstract: A transistor includes a first layer over a substrate. The transistor also includes a second layer over the first layer. The transistor further includes a carrier channel layer at an interface of the first layer and the second layer. The transistor additionally includes a gate structure, a drain, and a source over the second layer. The transistor also includes a passivation material in the second layer between an edge of the gate structure and an edge of the drain in a top-side view. The carrier channel layer has a smaller surface area than the first layer between the edge of the gate structure and the edge of the drain in the top-side view.

Abstract: A sensing device includes a MEMS sensor and an adjustable amplifier. The MEMS sensor is configured to generate an input signal according to environmental changes. The adjustable amplifier has a first input terminal, a second input terminal, a third input terminal, a fourth input terminal and a first output terminal. The first input terminal is electrically connected to the MEMS sensor for receiving the input signal. The second input terminal is electrically connected to a first signal terminal for receiving a first common-mode signal. The third input terminal is electrically connected to the first output terminal. The fourth input terminal is electrically connected to a second signal terminal. An electric potential of a first output signal output by the first output terminal of the adjustable amplifier is related to electric potentials of the input signal, the first signal terminal and the second signal terminal.

Abstract: A resistive random-access memory device formed on a semiconductor substrate includes an interlayer dielectric formed over the semiconductor substrate and includes a first via. A chemical-mechanical-polishing stop layer is formed over the interlayer dielectric. A lower metal layer formed in the first via presents a substantially planar top surface. A dielectric layer is formed over the chemical-mechanical-polishing stop layer and is in electrical contact with the lower metal layer. A barrier metal layer is formed over the dielectric layer. Edges of the dielectric layer and the first barrier metal layer form an aligned stack having edges extending beyond outer edges of the first via. A dielectric barrier layer including a second via is formed over the aligned stack and at least a portion of the chemical-mechanical-polishing stop layer. An upper metal layer formed in the second via in electrical contact with the barrier metal layer.

Abstract: A light emitting device includes a circuitry substrate and multiple light emitting diodes (LEDs) bonded to the circuitry substrate in a spaced array. The light emitting device also includes a continuous and substantially flat wavelength conversion member covering the light emitting diodes (LEDs) configured to convert the electromagnetic radiation emitted by the light emitting diodes (LEDs) into another wavelength range. The light emitting device also includes a planarized layer configured to support the wavelength conversion member on the circuitry substrate. The light emitting device can also include a light shaper on the wavelength conversion member configured to form emitting windows for the electromagnetic radiation transmitted through the wavelength conversion member forming an output light beam having a desired emitting window size, shape, and edge and to block and minimize scattered electromagnetic radiation from the wavelength conversion layer.

Abstract: A thin-film transistor array panel and a manufacturing method thereof are disclosed. The thin-film transistor array panel has a polysilicon layer including a first region, a second region and a third region. The second region includes a fourth region, a fifth region and a sixth region. The third region includes a seventh region, an eighth region and ninth region. The sixth, the fourth, the ninth and the seventh regions are doped with first, second, third and fourth ions, respectively. In a thin-film transistor of the thin-film transistor array panel, a gate electrode, a source electrode and a drain electrode thereof correspond to the first, the sixth and the ninth regions, respectively. The device is able to reduce leakage current in the thin-film transistor.

Abstract: A method of manufacturing a cross-point memory array device is disclosed. In the method, a substrate is provided. A plurality of first conductive line patterns are formed over the substrate. An insulating layer is formed over the first conductive line patterns. The insulating layer includes an insulative oxide. A plurality of switching film patterns are formed on the first conductive line patterns by selectively doping a plurality regions of the insulating layer. A plurality of memory structures are formed on the plurality of switching film patterns, respectively. A plurality of second conductive line patterns are formed on the plurality of memory structures.

Abstract: The present disclosure provides a semiconductor ESD protection device. The semiconductor ESD protection device includes a substrate including a first conductivity type, a gate formed on the substrate, a source region and a drain region formed in the substrate, and a body region formed in the substrate. The substrate and the body region include a first conductivity type. The source region and the drain region include a second conductivity type. And the first conductivity type and the second conductivity type are complementary to each other. The body region is electrically connected to the gate.

Abstract: An electronic component mounting board reduces shadows produced along its perimeter to improve the mountability of an electronic device and an electronic module. An electronic component mounting board (1) includes a substrate (2a) including a mount area (4) in which an electronic component (10) is mountable. The substrate (2a) includes electrode pads located at ends of the mount area (4) as viewed from above. The electronic component mounting board (1) includes a frame (2b) located outside the electrode pads (3) on the upper surface of the substrate (2a). The frame (2b) includes at least one side surface that slopes from an upper end to a lower end of the frame (2b), and flares from the upper end to the lower end as viewed from above.

Abstract: A flexible display and a method of manufacturing the same are disclosed. In one aspect, the display includes a flexible substrate including a display area and a peripheral area that surrounds the display area, and a thin-film transistor (TFT) layer formed on the flexible substrate and comprising an insulating layer and a TFT. The insulating layer is formed of an organic material and has an opening that surrounds the display area in the peripheral area; a pixel electrode electrically connected to the TFT. The display also includes a first metal layer formed in the opening and covering inner sides of the opening.