Patents Examined by Andy Huynh
  • Method of forming a nanosheet transistor
    Patent number: 10535733
    Abstract: A sacrificial gate stack for forming a nanosheet transistor includes a substrate. first, second and third silicon channel nanosheets formed over the substrate, and a first sandwich of germanium (Ge) containing layers disposed between the substrate and first silicon channel nanosheet. The stack also includes a second sandwich of Ge containing layers disposed between the first silicon channel nanosheet and the second silicon channel nanosheet; and a third sandwich of Ge containing layers disposed between the second silicon channel nanosheet and the third silicon channel nanosheet. Each sandwich includes first and second low Ge containing layers surrounding a silicon germanium (SiGe) sacrificial nanosheet that has a higher Ge concentration than the first and second low Ge containing layers.
    Type: Grant
    Filed: January 11, 2018
    Date of Patent: January 14, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kangguo Cheng, Choonghyun Lee, Juntao Li, Peng Xu
  • Display device
    Patent number: 10529747
    Abstract: A display device includes a first substrate including a display region and a non-display region, the non-display region being positioned on an outside of the display region, a first dam in the non-display region of the substrate, the first dam including a first barrier and a first stopper, the first stopper being on the first barrier and having a concave groove formed thereon, and a first alignment layer covering the display region of the first substrate, at least a part of the first alignment layer extending to the non-display region and contacting a surface of the first stopper.
    Type: Grant
    Filed: November 8, 2018
    Date of Patent: January 7, 2020
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Se Hee Han, Tae Gyun Kim
  • Techniques providing metal gate devices with multiple barrier layers
    Patent number: 10522544
    Abstract: A semiconductor device with a metal gate is disclosed. An exemplary semiconductor device with a metal gate includes a semiconductor substrate, source and drain features on the semiconductor substrate, a gate stack over the semiconductor substrate and disposed between the source and drain features. The gate stack includes a HK dielectric layer formed over the semiconductor substrate, a plurality of barrier layers of a metal compound formed on top of the HK dielectric layer, wherein each of the barrier layers has a different chemical composition; and a stack of metals gate layers deposited over the plurality of barrier layers.
    Type: Grant
    Filed: May 1, 2019
    Date of Patent: December 31, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Xiong-Fei Yu, Chun-Yuan Chou, Kuang-Yuan Hsu, Da-Yuan Lee, Jeff J. Xu
  • High electron mobility transistor structure and method of making the same
    Patent number: 10522630
    Abstract: A transistor includes a first layer over a substrate. The transistor also includes a second layer over the first layer. The transistor further includes a carrier channel layer at an interface of the first layer and the second layer. The transistor additionally includes a gate structure, a drain, and a source over the second layer. The transistor also includes a passivation material in the second layer between an edge of the gate structure and an edge of the drain in a top-side view. The carrier channel layer has a smaller surface area than the first layer between the edge of the gate structure and the edge of the drain in the top-side view.
    Type: Grant
    Filed: April 17, 2019
    Date of Patent: December 31, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Fu-Wei Yao, Chun-Wei Hsu, Chen-Ju Yu, Jiun-Lei Jerry Yu, Fu-Chih Yang, Chih-Wen Hsiung, King-Yuen Wong
  • Radial solder ball pattern for attaching semiconductor and micromechanical chips
    Patent number: 10515891
    Abstract: A radial solder ball pattern is described for a printed circuit board and for a chip to be attached to the printed circuit board is described. In one example, the pattern comprises a central power connector area having a plurality of power connectors to provide power to an attached chip, a signal area having a plurality of signal connectors to communicate signals to the attached chip, an edge area surrounding the signal area and the central power connector area, and a plurality of traces each coupled to a signal connector, the traces extending from the respective coupled signal connector away from the central power connector to connect to an external component, wherein the signal connectors are placed in rows, the rows having a greater separation near the edge area than near the central area.
    Type: Grant
    Filed: October 4, 2018
    Date of Patent: December 24, 2019
    Assignee: Intel Corporation
    Inventors: Eng Fook Chan, Wei Chung Lee, Zhi Wei Low
  • Raised epitaxial LDD in MuGFETs and methods for forming the same
    Patent number: 10516024
    Abstract: Embodiments include Multiple Gate Field-Effect Transistors (MuGFETs) and methods of forming them. In an embodiment, a structure includes a substrate, a fin, masking dielectric layer portions, and a raised epitaxial lightly doped source/drain (LDD) region. The substrate includes the fin. The masking dielectric layer portions are along sidewalls of the fin. An upper portion of the fin protrudes from the masking dielectric layer portions. A first spacer is along a sidewall of a gate structure over a channel region of the fin. A second spacer is along the first spacer. The raised epitaxial LDD region is on the upper portion of the fin, and the raised epitaxial LDD region adjoins a sidewall of the first spacer and is disposed under the second spacer. The raised epitaxial LDD region extends from the upper portion of the fin in at least two laterally opposed directions and a vertical direction.
    Type: Grant
    Filed: April 3, 2018
    Date of Patent: December 24, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yong-Yan Lu, Hou-Yu Chen, Shyh-Horng Yang
  • Semiconductor devices, methods of manufacturing thereof, and image sensor devices
    Patent number: 10515994
    Abstract: Semiconductor devices, methods of manufacturing thereof, and image sensor devices are disclosed. In some embodiments, a semiconductor device comprises a semiconductor chip comprising an array region, a periphery region, and a through-via disposed therein. The semiconductor device comprises a guard structure disposed in the semiconductor chip between the array region and the through-via or between the through-via and a portion of the periphery region.
    Type: Grant
    Filed: October 1, 2018
    Date of Patent: December 24, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventors: Chun-Chieh Chuang, Dun-Nian Yaung, Jen-Cheng Liu, Tzu-Hsuan Hsu, Feng-Chi Hung, Min-Feng Kao
  • Semiconductor device including vertical routing structure and method for manufacturing the same
    Patent number: 10515948
    Abstract: A method includes forming a transistor having source and drain regions. The following are formed on the source/drain region: a first via, a first metal layer extending along a first direction on the first via, a second via overlapping the first via on the first metal layer, and a second metal extending along a second direction different from the first direction on the second via; and the following are formed on the drain/source region: a third via, a third metal layer on the third via, a fourth via overlapping the third via over the third metal layer, and a controlled device at a same height level as the second metal layer on the third metal layer.
    Type: Grant
    Filed: March 30, 2018
    Date of Patent: December 24, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Wei-Chih Wen, Han-Ting Tsai, Chung-Te Lin
  • Semiconductor device
    Patent number: 10510700
    Abstract: Disclosed is a semiconductor device suppressed in decrease of reliability. The semiconductor device comprises an electrode pad portion (2) formed on the upper surface of a semiconductor substrate (1), a passivation layer (3) so formed on the upper surface of the semiconductor substrate (1) as to overlap a part of the electrode pad portion (2) and having a first opening portion (3a) where the upper surface of the electrode pad portion (2) is exposed, a barrier metal layer (5) formed on the electrode pad portion (2), and a solder bump (6) formed on the barrier metal layer (5). The barrier metal layer (5) is formed such that an outer peripheral end (5b) lies within the first opening portion (3a) of the passivation layer (3) when viewed in plan.
    Type: Grant
    Filed: June 26, 2018
    Date of Patent: December 17, 2019
    Assignee: Rohm Co., Ltd.
    Inventors: Tadahiro Morifuji, Shigeyuki Ueda
  • Flash memory structure with reduced dimension of gate structure and methods of forming thereof
    Patent number: 10510766
    Abstract: A method for forming a semiconductor memory device structure includes forming a select gate structure and a dielectric layer, forming a charge trapping layer along a sidewall of a lower portion of the select gate structure and a sidewall of the dielectric layer, and forming a memory gate structure over the charge trapping layer. The select gate structure and the memory gate structure contact opposing sidewalls of the charge trapping layer. The dielectric layer is interposed between the charge trapping layer and the select gate structure.
    Type: Grant
    Filed: May 24, 2019
    Date of Patent: December 17, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO,. LTD.
    Inventors: Sheng-Chieh Chen, Ming Chyi Liu, Shih-Chang Liu
  • Fan-out package structure and method
    Patent number: 10510648
    Abstract: A method comprises embedding a semiconductor structure in a molding compound layer, depositing a plurality of photo-sensitive material layers over the molding compound layer, developing the plurality of photo-sensitive material layers to form a plurality of openings, wherein a first portion and a second portion of an opening of the plurality of openings are formed in different photo-sensitive material layers and filling the first portion and the second portion of the opening with a conductive material to form a first via in the first portion and a first redistribution layer in the second portion.
    Type: Grant
    Filed: December 18, 2018
    Date of Patent: December 17, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tzu-Wei Chiu, Sao-Ling Chiu
  • Pad structure and manufacturing method thereof in semiconductor device
    Patent number: 10510696
    Abstract: A method of manufacturing a semiconductor device includes: forming a memory cell on a substrate; forming a conductive pad region to electrically couple to the memory cell; depositing a dielectric layer over the conductive pad region; forming a first passivation layer over the dielectric layer; etching the first passivation layer through the dielectric layer, thereby exposing a first area of the conductive pad region; forming a second passivation layer over the first passivation layer and the exposed first area of the conductive pad region; and etching the second passivation layer to expose a second area of the conductive pad region.
    Type: Grant
    Filed: April 25, 2018
    Date of Patent: December 17, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Hung-Shu Huang, Ming-Chyi Liu
  • Semiconductor memory device and method for fabricating the same
    Patent number: 10510803
    Abstract: A method for fabricating a semiconductor memory device is provided. The method includes: etching a first region of the semiconductor memory device to expose a first capping layer; forming a second capping layer on the first capping layer; etching a portion of the first capping layer and a portion of the second capping layer to form a first trench reaching a first metal line; and forming a second metal line in the first trench to contact the first metal line.
    Type: Grant
    Filed: July 20, 2018
    Date of Patent: December 17, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Harry-Hak-Lay Chuang, Sheng-Huang Huang, Shih-Chang Liu, Chern-Yow Hsu
  • Molded chip combination
    Patent number: 10510721
    Abstract: Various molded chip combinations and methods of manufacturing the same are disclosed. In one aspect, a molded chip combination is provided that includes a first semiconductor chip that has a first PHY region, a second semiconductor chip that has a second PHY region, an interconnect chip interconnecting the first PHY region to the second PHY region, and a molding joining together the first semiconductor chip, the second semiconductor chip and the interconnect chip.
    Type: Grant
    Filed: August 11, 2017
    Date of Patent: December 17, 2019
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Milind S. Bhagavat, Lei Fu, Ivor Barber, Chia-Ken Leong, Rahul Agarwal
  • Insulated gate bipolar transistors and fabrication methods thereof
    Patent number: 10505012
    Abstract: An insulated gate bipolar transistor (IGBT) includes a substrate, including a device region and a collection region, arranged into a bilayer structure. The device region includes a plurality of control regions and a plurality of turn-off regions. The IGBT also includes a drift region formed in the control regions and the turn-off regions, and electrically connected to the collection region; a well region formed in the control regions and the turn-off regions, and in contact with the drift region; a plurality of first gate structures formed in the control regions, and in contact with the drift region and the well region; and a plurality of emission regions formed in the well region of the control regions, and on at least one side of each first gate structure. The emission regions are isolated from the drift region, and are electrically connected to the well region of the turn-off regions.
    Type: Grant
    Filed: January 29, 2018
    Date of Patent: December 10, 2019
    Assignees: Semiconductor Manufacturing International (Shanghai) Corporation, Semiconducor Manufacturing International (Beijing) Corporation
    Inventor: Lei Bing Yuan
  • Array substrate and display device
    Patent number: 10488714
    Abstract: The present disclosure discloses an array substrate and a display device. A pixel electrode of the array substrate includes a first subpixel electrode and a second subpixel electrode, and a storage capacitor includes a first storage capacitor and a second storage capacitor, wherein the first storage capacitor is configured to maintain a voltage difference between the first subpixel electrode and the common electrode line, the second storage capacitor is configured to maintain a voltage difference between the second subpixel electrode and the common electrode line, and the first storage capacitor and the second storage capacitor have different capacitances.
    Type: Grant
    Filed: July 27, 2017
    Date of Patent: November 26, 2019
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Pan Li, Wenbo Li, Hongfei Cheng
  • Silicon carbide semiconductor device and method of manufacturing silicon carbide semiconductor device
    Patent number: 10490625
    Abstract: A silicon carbide semiconductor device includes a silicon carbide semiconductor substrate, a first semiconductor layer, a first semiconductor region, a second semiconductor layer, a second semiconductor region, a third semiconductor region, a fourth semiconductor sub-region, a first electrode, a gate insulating film, a gate electrode, and second electrode. At a corner part of an active region in which a main current flows, a fifth semiconductor sub-region is provided. An impurity concentration of the fifth semiconductor sub-region is higher than an impurity concentration of the second semiconductor layer.
    Type: Grant
    Filed: March 30, 2018
    Date of Patent: November 26, 2019
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Shin'ichi Nakamata, Takashi Shiigi, Yasuyuki Hoshi, Yuichi Harada
  • Display device and method for manufacturing the same
    Patent number: 10490668
    Abstract: Provided are a display device and a method for manufacturing the same. The display device includes: a connection source electrode and a connection drain electrode connected to a first source electrode a the first drain electrode, respectively by penetrating an isolation insulating layer and a second interlayer dielectric layer to enhance a characteristic of an element and reliability of the display device.
    Type: Grant
    Filed: October 26, 2017
    Date of Patent: November 26, 2019
    Assignee: LG Display Co., Ltd.
    Inventors: SoYoung Noh, YoungJang Lee, HyoJin Kim, Hyuk Ji
  • Tip-contact controlled three dimensional (3D) vertical self select memory
    Patent number: 10475995
    Abstract: A variable resistance memory cell with a wide difference (“window”) between threshold voltages is provided. The window between threshold voltages is increased by amplifying the stoichiometry gradient by means of an asymmetry in the memory cell architecture to provide a greater margin for detecting different logic states of the memory cell.
    Type: Grant
    Filed: December 22, 2017
    Date of Patent: November 12, 2019
    Assignee: Intel Corporation
    Inventor: Paolo Fantini
  • Transistor structure and method for fabricating the same
    Patent number: 10475932
    Abstract: A transistor structure includes a first oxide semiconductor layer, a source structure and a drain structure, and a second oxide semiconductor layer. The first oxide semiconductor layer is doped with sulfur. The source structure and the drain structure are disposed on the first oxide semiconductor layer, and a region of the first oxide semiconductor layer between the source structure and the drain structure forms a channel region. The second oxide semiconductor layer doped with sulfur is at least formed on the channel region of the first oxide semiconductor layer.
    Type: Grant
    Filed: November 30, 2017
    Date of Patent: November 12, 2019
    Assignee: Untied Microelectronics Corp.
    Inventors: Shao-Hui Wu, Yu-Cheng Tung