Patents Examined by Anh D. Mai
  • Patent number: 11979992
    Abstract: An electronic medical device is disclosed here. An exemplary embodiment of the medical device includes a printed circuit board assembly, a protective inner shell surrounding at least a portion of the printed circuit board assembly, and an outer shell surrounding at least a portion of the protective inner shell. The printed circuit board assembly has a printed circuit board, electronic components mounted to the printed circuit board, a battery mounted to the printed circuit board, and an interface compatible with a physiological characteristic sensor component. The protective inner shell is formed by overmolding the printed circuit board assembly with a first material having low pressure and low temperature molding properties. The outer shell is formed by overmolding the protective inner shell with a second material that is different than the first material.
    Type: Grant
    Filed: August 24, 2021
    Date of Patent: May 7, 2024
    Assignee: Medtronic MiniMed, Inc.
    Inventors: Claire F. Ferraro, Shelley L. Thurk, Mark Henschel, Shawn Shi, Gabe German
  • Patent number: 11968828
    Abstract: A semiconductor device is provided. The semiconductor device includes a semiconductor substrate and a first gate stack. An isolation feature is formed in the semiconductor substrate, and a cell region and a peripheral region adjacent to the cell region are defined in the semiconductor substrate. The first gate stack is disposed on the peripheral region of the semiconductor substrate. The first gate stack includes a first dielectric layer and a gate electrode layer disposed on the first dielectric layer and covering a top surface of the first dielectric layer. The first dielectric layer is disposed on the semiconductor substrate and has a concave profile.
    Type: Grant
    Filed: July 9, 2019
    Date of Patent: April 23, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Meng-Han Lin, Wen-Tuo Huang, Yong-Shiuan Tsair
  • Patent number: 11956937
    Abstract: A semiconductor device can include a field insulating film on a substrate and a fin-type pattern of a particular material, on the substrate, having a first sidewall and an opposing second sidewall. The fin-type pattern can include a first portion of the fin-type pattern that protrudes from an upper surface of the field insulating film and a second portion of the fin-type pattern disposed on the first portion. A third portion of the fin-type pattern can be disposed on the second portion where the third portion can be capped by a top rounded surface of the fin-type pattern and the first sidewall can have an undulated profile that spans the first, second and third portions.
    Type: Grant
    Filed: January 24, 2020
    Date of Patent: April 9, 2024
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Ki-Il Kim, Jung-Gun You, Gi-Gwan Park
  • Patent number: 11948964
    Abstract: An image sensor is disclosed. The image sensor includes a semiconductor substrate, a plurality of pillars protruding from the semiconductor substrate, and spaced from each other, a spacer layer on the semiconductor substrate and a sidewall of each of the plurality of pillars, a plurality of gate structures on the spacer layer, and a plurality of unit pixels arranged in a matrix form. The first unit pixel includes a first photodiode (PD) formed in the semiconductor substrate, a first pillar, a second pillar and a third pillar of the plurality of pillars, and a first gate structure and a second gate structure of the plurality of gate structures. Each of the first pillar and the second pillar includes a first channel region and a first drain region on the first channel region. The third pillar is not surround by any gate structure of the plurality of gate structures.
    Type: Grant
    Filed: June 18, 2020
    Date of Patent: April 2, 2024
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Kangmook Lim, Sungin Kim, Changhwa Kim, Yeoseon Choi
  • Patent number: 11925017
    Abstract: A semiconductor device is provided. The semiconductor device includes a substrate, a stacked gate structure, and a wall structure. The stacked gate structure is on the substrate and extending along a first direction. The wall structure is on the substrate and laterally aside the stacked gate structure. The wall structure extends along the first direction and a second direction perpendicular to the first direction. The stacked gate structure is overlapped with the wall structure in the first direction and the second direction.
    Type: Grant
    Filed: January 13, 2020
    Date of Patent: March 5, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chien-Hsuan Liu, Chiang-Ming Chuang, Chih-Ming Lee, Kun-Tsang Chuang, Hung-Che Liao, Chia-Ming Pan, Hsin-Chi Chen
  • Patent number: 11862678
    Abstract: A pixel-array substrate includes a semiconductor substrate with a pixel array, a back surface, and a front surface, and a guard ring formed of a doped semiconductor, enclosing the pixel array, and extending into the semiconductor substrate from the front surface, the back surface forming a trench extending into the semiconductor substrate, the trench overlapping the guard ring. A method for reducing leakage current into a pixel-array includes doping a semiconductor substrate to form a guard ring that extends into the semiconductor substrate from a front surface, encloses a pixel array, excludes a periphery region, and resists a flow of electric current, and forming, into a back surface of the semiconductor substrate, a trench that penetrates into the back surface and overlaps the guard ring, the guard ring and the trench configured to resist the flow of electric current between the pixel array and the periphery region.
    Type: Grant
    Filed: June 18, 2020
    Date of Patent: January 2, 2024
    Assignee: OmniVision Technologies, Inc.
    Inventors: Yuanwei Zheng, Sing-Chung Hu, Gang Chen, Dyson Tai, Lindsay Grant
  • Patent number: 11854990
    Abstract: A device includes an interposer, which includes a substrate having a top surface. An interconnect structure is formed over the top surface of the substrate, wherein the interconnect structure includes at least one dielectric layer, and metal features in the at least one dielectric layer. A plurality of through-substrate vias (TSVs) is in the substrate and electrically coupled to the interconnect structure. A first die is over and bonded onto the interposer. A second die is bonded onto the interposer, wherein the second die is under the interconnect structure.
    Type: Grant
    Filed: February 16, 2021
    Date of Patent: December 26, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Hsien-Pin Hu, Chen-Hua Yu, Ming-Fa Chen, Jing-Cheng Lin, Jiun Ren Lai, Yung-Chi Lin
  • Patent number: 11844235
    Abstract: An organic light emitting display device includes a substrate comprising a display area and a peripheral area and a first reflective member positioned in both the display area and the peripheral area. The first reflective member includes a first opening formed in a light-emitting region of the display area and a second opening formed in the peripheral area. The second reflective portion has openings having the same shape as openings formed in the first reflective portion. Thus, a reflectivity of the first reflective portion may be substantially the same as a reflectivity of the second reflective portion, and the first reflective portion and the second reflective portion may be perceived as an integral reflective member. Therefore, a bezel-less mirror organic light emitting display device may be manufactured.
    Type: Grant
    Filed: February 10, 2017
    Date of Patent: December 12, 2023
    Assignee: Samsung Display Co., Ltd.
    Inventors: Joonyoup Kim, Youngwoo Song, Jinkoo Chung, Junho Choi
  • Patent number: 11824085
    Abstract: Provided is a semiconductor device including: an N-type diffusion layer being a second region, formed in a surface portion of a P-type diffusion layer being a first region, to function as a RESURF region; an N-type buried diffusion layer being a third region formed in a bottom portion of the second region, close to a high-side circuit; and a MOSFET using the second region as a drift layer. The MOSFET includes a thermal oxide film formed between an N-type diffusion layer being a fourth region serving as a drain region and an N-type diffusion layer being a sixth region serving as a source region, and an N-type diffusion layer being a seventh region formed below the thermal oxide film. The seventh region has an end portion close to a low-side circuit, being closer to the low-side circuit than an end portion of the third region close to the low-side circuit.
    Type: Grant
    Filed: October 20, 2020
    Date of Patent: November 21, 2023
    Assignee: Mitsubishi Electric Corporation
    Inventors: Toshihiro Imasaka, Kazuhiro Shimizu, Manabu Yoshino, Yuji Kawasaki
  • Patent number: 11818913
    Abstract: An organic light-emitting diode (OLED) display and a method of manufacturing the same are disclosed. In one aspect, the display includes a lower substrate with a display area and a peripheral area surrounding the display area, an upper substrate facing the lower substrate and a display unit disposed on the display area. The display also includes a sealant disposed on the peripheral area and sealing the lower and upper substrates and a first metal layer interposed between the lower substrate and the sealant. The first metal layer includes a plurality of first through-portions extending in a first direction and arranged in a second direction crossing the first direction. The display also includes a second metal layer disposed on the first metal layer and comprising a plurality of second through-portions respectively corresponding to the first through-portions.
    Type: Grant
    Filed: May 9, 2022
    Date of Patent: November 14, 2023
    Assignee: Samsung Display Co., Ltd.
    Inventor: Junyong An
  • Patent number: 11744115
    Abstract: A display panel having a pixel defining layer defining subpixel apertures of subpixels is provided. The pixel defining layer is a unitary structure including column portions and row portions. A respective row portion is between two adjacent subpixel apertures that are in a same column and respectively from two adjacent rows. A respective column portion is in a space between two adjacent columns of subpixel apertures, spacing apart multiple pairs of adjacent row portions respectively in multiple rows. A respective row portion includes a depression part configured to allow fluid communication of an ink solution between the two adjacent subpixel apertures in the same column and respectively from the two adjacent rows. A minimum height of the depression part relative to a base substrate is less than a minimum height of a column portion adjacent to the respective row portion relative to the base substrate.
    Type: Grant
    Filed: May 17, 2021
    Date of Patent: August 29, 2023
    Assignee: BOE Technology Group Co., Ltd.
    Inventor: Dejiang Zhao
  • Patent number: 11737354
    Abstract: Provided is an organic light emitting device having between the cathode and a light emitting layer an an organic material layer containing a compound of any one of the following Chemical Formulae 1-2 to 1-4: wherein: X1 to X3 are each independently N or CH, and at least one of X1 to X3 is N; L1 is a substituted or unsubstituted monocyclic arylene group having 6 to 24 carbon atoms; Ar1 and Ar2 are the same as or different from each other, and are each independently a substituted or unsubstituted monocyclic or polycyclic aryl group having 6 to 20 carbon atoms; and Z1 is deuterium; and an organic material layer provided between the anode and the light emitting layer and including a spirobifluorene-monoamine based compound of Chemical Formula 2:
    Type: Grant
    Filed: May 29, 2020
    Date of Patent: August 22, 2023
    Assignee: LG CHEM, LTD.
    Inventors: Jungoh Huh, Dong Hoon Lee
  • Patent number: 11737362
    Abstract: An apparatus includes a first semiconductor fin and a second semiconductor fin that is parallel to the first semiconductor fin. The first semiconductor fin extends from a first region of a substrate near a circuit that produces thermal energy when a circuit is in operation to a second region of the substrate, which is disposed away from the circuit. The second semiconductor fin extends from the first region to the second region and has a different material composition than the first semiconductor fin. The first and second semiconductor fins collectively exhibit a Seebeck effect when the circuit is in operation. The apparatus includes interconnects to couple the first and second semiconductor fins to a power supply circuit to transfer electricity generated due to the Seebeck effect to the power supply circuit.
    Type: Grant
    Filed: April 1, 2016
    Date of Patent: August 22, 2023
    Assignee: Intel Corporation
    Inventors: Kinyip Phoa, Jui-Yen Lin, Nidhi Nidhi, Chia-Hong Jan
  • Patent number: 11728292
    Abstract: The invention provides a semiconductor package assembly. The semiconductor package assembly includes a first semiconductor package including a first redistribution layer (RDL) structure having a first surface and a second surface opposite to the first substrate. The first RDL structure includes a plurality of first conductive traces close to the first surface of the first RDL structure. An antenna pattern is disposed close to the second surface of the first RDL structure. A first semiconductor die is disposed on the first surface of the first RDL structure and electrically coupled to the first RDL structure. A plurality of conductive structures is disposed on the first surface of the first RDL structure and electrically coupled to the first RDL structure. The plurality of conductive structures is spaced apart from the antenna pattern through the plurality of first conductive traces of the first RDL structure.
    Type: Grant
    Filed: January 31, 2020
    Date of Patent: August 15, 2023
    Assignee: MediaTek Inc.
    Inventors: Tzu-Hung Lin, I-Hsuan Peng, Nai-Wei Liu, Wei-Che Huang, Che-Ya Chou
  • Patent number: 11706935
    Abstract: An electroluminescent device, a method for fabricating the same, a display panel, and a display device are disclosed. The electroluminescent device includes a hole inject layer, a hole transport layer, an electron transport layer, and an electron inject layer. At least one of the hole inject layer, the hole transport layer, the electron transport layer, and electron inject layer is a target film including a small molecular layer and a large molecular layer which are arranged in a stacked manner.
    Type: Grant
    Filed: March 8, 2019
    Date of Patent: July 18, 2023
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventor: Wenjun Hou
  • Patent number: 11688775
    Abstract: A method of forming a semiconductor structure includes forming at least one fin disposed over a top surface of a substrate, the fin providing a vertical transport channel for a vertical transport field-effect transistor. The method also includes forming a top source/drain region disposed over a top surface of the fin, and forming a first contact trench at a first end of the fin and a second contact trench at a second end of the fin, the first and second contact trenches being self-aligned to the top source/drain region. The method further includes forming inner spacers on sidewalls of the first contact trench and the second contact trench, and forming contact material in the first contact trench and the second contact trench between the inner spacers. The contact material comprises a stressor material that induces vertical strain in the fin.
    Type: Grant
    Filed: August 13, 2018
    Date of Patent: June 27, 2023
    Assignee: International Business Machines Corporation
    Inventors: Juntao Li, Kangguo Cheng, Brent A. Anderson
  • Patent number: 11637186
    Abstract: Semiconductor devices and methods of forming the same are provided. In one embodiment, a semiconductor device according to the present disclosure includes a fin extending from a substrate, a gate structure over a channel region of the fin, a source/drain contact over a source/drain region of the fin, a gate cut feature adjacent the gate structure, a source/drain contact isolation feature adjacent the source/drain contact, a spacer extending along a sidewall of the gate cut feature and a sidewall of the gate structure, a liner extending along a sidewall of the source/drain contact isolation feature and a sidewall of the source/drain contact; and an air gap sandwiched between the spacer and the liner. The gate cut feature and the source/drain contact isolation feature are separated by the spacer, the air gap and the liner.
    Type: Grant
    Filed: May 8, 2019
    Date of Patent: April 25, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Jia-Chuan You, Chia-Hao Chang, Tien-Lu Lin, Yu-Ming Lin, Chih-Hao Wang
  • Patent number: 11621279
    Abstract: A semiconductor device includes a semiconductor layer, a transistor cell portion, formed in the semiconductor layer, a first trench, formed in the semiconductor layer, a diode, electrically separated from the transistor cell portion and having a first conductivity type portion and a second conductivity type portion disposed inside the first trench, a second trench, formed in the semiconductor layer, and a bidirectional Zener diode, electrically connected to the transistor cell portion and having a pair of first conductivity type portions, disposed inside the second trench, and at least one second conductivity type portion, formed between the pair of first conductivity type portion.
    Type: Grant
    Filed: May 29, 2019
    Date of Patent: April 4, 2023
    Assignee: ROHM CO., LTD.
    Inventor: Ryuta Yaginuma
  • Patent number: 11616205
    Abstract: A flexible display apparatus includes a flexible display panel configured to wind around a winding axis unit, and a cushion unit arranged on the flexible display panel, wherein the cushion unit is arranged on a surface of the flexible display panel facing a circumferential surface of the winding axis unit.
    Type: Grant
    Filed: July 1, 2019
    Date of Patent: March 28, 2023
    Assignee: Samsung Display Co., Ltd.
    Inventor: Dongwook Choi
  • Patent number: 11563051
    Abstract: The present application provides a light-emitting diode (LED) light board, a spliced LED light board and a display device. The LED light board includes a substrate, a plurality of LED chips, and a gate driving module; the LED chip array is arranged on the substrate; the gate driving module is disposed on the substrate and configured to provide a gate driving signal to the LED chips, the gate driving module includes a plurality of gate driving units; the LED chips are arranged on opposite sides of the gate driving module, and each of the gate driving units is electrically connected to its corresponding ones of the LED chips on opposite sides of the gate driving unit.
    Type: Grant
    Filed: August 17, 2020
    Date of Patent: January 24, 2023
    Assignee: WUHAN CHINA STAR OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventor: Fancheng Liu