Abstract: The present application provides a light-emitting diode (LED) light board, a spliced LED light board and a display device. The LED light board includes a substrate, a plurality of LED chips, and a gate driving module; the LED chip array is arranged on the substrate; the gate driving module is disposed on the substrate and configured to provide a gate driving signal to the LED chips, the gate driving module includes a plurality of gate driving units; the LED chips are arranged on opposite sides of the gate driving module, and each of the gate driving units is electrically connected to its corresponding ones of the LED chips on opposite sides of the gate driving unit.

Abstract: A semiconductor device of the present invention includes a semiconductor region having a first main surface, wherein the semiconductor region includes: alternating n-type pillar layers and p-type pillar layers along the first main surface; a p-type first well layer located within each of the n-type pillar layers at a top surface of the n-type pillar layer; an n-type first source layer located within the first well layer at a top surface of the first well layer; a first side surface dielectric layer located on a side surface in a first trench located at each of boundaries between the n-type pillar layers and the p-type pillar layers, and being in contact with the first well layer and the first source layer; a first bottom surface dielectric layer located on a bottom surface in the first trench, and being at least partially in contact with one of the p-type pillar layers.

Abstract: A semiconductor device includes a first switching element; a second switching element; a first metal member; a second metal member; a first terminal that has a potential on a high potential side; a second terminal that has a potential on a low potential side; a third terminal that has a midpoint potential; and a resin part. A first potential part has potential equal to potential of the first terminal. A second potential part has potential equal to potential of the second terminal. A third potential part has potential equal to potential of the third terminal. A first creepage distance between the first potential part and the second potential part is longer than a minimum value of a second creepage distance between the first potential part and the third potential part and a third creepage distance between the second potential part and the third potential part.

Abstract: According to an exemplary embodiment of the present invention, a display device includes a base substrate provided with light emitting elements, an encapsulation layer covering the light emitting elements, a first conductive layer disposed on the encapsulation layer and comprising first conductive patterns, a first insulation layer disposed on the encapsulation layer to cover the first conductive patterns, a second conductive layer disposed on the first insulation layer and comprising first sensing patterns, second conductive patterns electrically connecting the first sensing patterns, and second sensing patterns electrically connected by the first conductive patterns, a second insulation layer disposed on the first insulation layer and the second conductive layer without overlapping the light emitting elements to cover the second conductive layer, and a light shielding layer covering the second insulation layer.

Abstract: A method for manufacturing a semiconductor device includes forming a plurality of fins on a semiconductor substrate. In the method, sacrificial spacer layers are formed on the plurality of fins, and portions of the semiconductor substrate located under the sacrificial spacer layers and located at sides of the plurality of fins are removed. Bottom source/drain regions are grown in at least part of an area where the portions of the semiconductor substrate were removed, and sacrificial epitaxial layers are grown on the bottom source/drain regions. The method also includes diffusing dopants from the bottom source/drain regions and the sacrificial epitaxial layers into portions of the semiconductor substrate under the plurality of fins. The sacrificial epitaxial layers are removed, and bottom spacers are formed in at least part of an area where the sacrificial epitaxial layers were removed.

Abstract: A crystal substrate 1 includes an underlying layer 2 and a thick film 3. The underlying layer 2 is composed of a crystal of a nitride of a group 13 element and includes a first main face 2a and a second main face 2b. The thick film 3 is composed of a crystal of a nitride of a group 13 element and provided over the first main face of the underlying layer. The underlying layer 2 includes a low carrier concentration region 5 and a high carrier concentration region 4 both extending between the first main face 2a and the second main face 2b.

Abstract: A semiconductor device package includes a first substrate, an antenna, a support layer, a dielectric layer and a second substrate. The first substrate has a first surface and a second surface opposite to the first surface. The antenna element is disposed on the second surface of the first substrate. The support layer is disposed on the first surface of the first substrate and at the periphery of the first surface of the first substrate. The support layer has a first surface facing away from the first substrate. The dielectric layer is disposed on the first surface of the support layer and spaced apart from the first substrate. The dielectric layer is chemically bonded to the support layer. The second substrate is disposed on a first surface of the dielectric layer facing away from the support layer.

Abstract: A transistor device includes transistor cells each having source and drift regions of a first doping type and a body region of a second doping type in a first region of a semiconductor body, and a gate electrode dielectrically insulated from the body region. A gate conductor arranged on top of a second region of the semiconductor body is electrically connected to each gate electrode. A source conductor arranged on top of the first region is connected to each source and body region. A discharging region of the second doping type is arranged in the second region and located at least partially below the gate conductor, and includes at least one lower dose section in which a doping dose is lower than a minimum doping dose in other sections of the discharging region. The at least one lower dose section is associated with a corner of the gate conductor.

Abstract: Chip packages and methods of forming a chip package. The chip package includes a power amplifier and a thermal pathway structure configured to influence transport of heat energy. The power amplifier includes a first emitter finger and a second emitter finger having at least one parameter that is selected based upon proximity to the thermal pathway structure.

Abstract: A vertical memory device includes a lower circuit pattern on a substrate, a plurality of gate electrodes spaced apart from another in a first direction substantially perpendicular to an upper surface of the substrate on the lower circuit pattern, a channel extending through the gate electrodes in the first direction, a memory cell block including a first common source line (CSL) extending in a second direction substantially parallel to the upper surface of the substrate, and a first contact plug connected to the lower circuit pattern and the first CSL and overlapping the first CSL in the first direction.

Abstract: An organic light-emitting diode (OLED) display and a method of manufacturing the same are disclosed. In one aspect, the display includes a lower substrate with a display area and a peripheral area surrounding the display area, an upper substrate facing the lower substrate and a display unit disposed on the display area. The display also includes a sealant disposed on the peripheral area and sealing the lower and upper substrates and a first metal layer interposed between the lower substrate and the sealant. The first metal layer includes a plurality of first through-portions extending in a first direction and arranged in a second direction crossing the first direction. The display also includes a second metal layer disposed on the first metal layer and comprising a plurality of second through-portions respectively corresponding to the first through-portions.

Abstract: A solid-state imaging device includes: a first photodiode made up of a first first-electroconductive-type semiconductor region formed on a first principal face side of a semiconductor substrate, and a first second-electroconductive-type semiconductor region formed within the semiconductor substrate adjacent to the first first-electroconductive-type semiconductor region; a second photodiode made up of a second first-electroconductive-type semiconductor region formed on a second principal face side of the semiconductor substrate, and a second second-electroconductive-type semiconductor region formed within the semiconductor substrate adjacent to the second first-electroconductive-type semiconductor region; and a gate electrode formed on the first principal face side of the semiconductor substrate; with impurity concentration of a connection face between the second first-electroconductive-type semiconductor region and the second second-electroconductive-type semiconductor region being equal to or greater than im

Abstract: A high electron mobility transistor (HEMT) device including a substrate, a first channel layer, a second channel layer, a cap layer, a first metal nitride layer, a gate, a source, and a drain is provided. The first channel layer is disposed on the substrate. The second channel layer is disposed on the first channel layer. The cap layer is disposed on the second channel layer and exposes a portion of the second channel layer. The first metal nitride layer is disposed on the cap layer. The gate is disposed on the first metal nitride layer. The width of the first metal nitride layer is greater than or equal to the width of the gate. The source and the drain are disposed on the second channel layer at two sides of the gate.

Abstract: A transistor device includes a channel, a first source/drain region positioned on a first side of the channel, a second source/drain region positioned on a second side of the channel opposite the first side of the channel, and a tunnel barrier disposed between the channel and the first source/drain region, the tunnel barrier adapted to suppress band-to-band tunneling while the transistor device is in an off state.

Abstract: A silicon carbide semiconductor device includes a first semiconductor layer of a first conductivity type provided on a front surface of a semiconductor substrate of the first conductivity type; a second semiconductor layer of a second conductivity type; a first semiconductor region of the first conductivity type; and a gate electrode having a striped-shape and provided on a gate insulating film. The silicon carbide semiconductor device further includes a first electrode provided on a surface of the second semiconductor layer and the first semiconductor region; a step film provided on the first electrode; a plating film provided on the first electrode and the step film; and a solder on the plating film. The step film is provided on the first electrode on which the solder and the plating film are provided, the step film being provided so as to be embedded in grooves formed on the first electrode.

Abstract: Channel engineering is employed to obtain a gate-all-around field-effect transistor having an asymmetric threshold voltage. A dual channel profile enables a steep potential distribution near the source side that enhances the lateral channel electric field and thus increases the carrier mobility.

Abstract: A method of manufacturing a semiconductor device includes providing a substrate including a first region and a second region, forming a first channel layer in the first region of the substrate, forming an isolation region in the substrate to electrically isolate a portion of the first region from a portion of the second region, etching an upper surface of the second region of the substrate, forming a protection layer covering the first channel layer in the first region of the substrate and the second region of the substrate, removing the protection layer on the second region of the substrate, forming a gate insulation material layer on the protection layer and on the second region of the substrate, and removing the gate insulation material layer and the protection layer on the first region of the substrate.

Abstract: A micro-electromechanical device and method of manufacture are disclosed. A sacrificial layer is formed on a silicon substrate. A metal layer is formed on a top surface of the sacrificial layer. Soft magnetic material is electrolessly deposited on the metal layer to manufacture the micro-electromechanical device. The sacrificial layer is removed to produce a metal beam separated from the silicon substrate by a space.

Abstract: An electronic medical device is disclosed here. An exemplary embodiment of the medical device includes a printed circuit board assembly, a protective inner shell surrounding at least a portion of the printed circuit board assembly, and an outer shell surrounding at least a portion of the protective inner shell. The printed circuit board assembly has a printed circuit board, electronic components mounted to the printed circuit board, a battery mounted to the printed circuit board, and an interface compatible with a physiological characteristic sensor component. The protective inner shell is formed by overmolding the printed circuit board assembly with a first material having low pressure and low temperature molding properties. The outer shell is formed by overmolding the protective inner shell with a second material that is different than the first material.

Abstract: An edge delimits a semiconductor body in a direction parallel to a first side of the semiconductor body. A peripheral area is arranged between the active area and edge. A first semiconductor region of a first conductivity type extends from the active area into the peripheral area. A second semiconductor region of a second conductivity type forms a pn-junction with the first semiconductor region. A first edge termination region of the second conductivity type arranged at the first side adjoins the first semiconductor region, between the second semiconductor region and edge. A second edge termination region of the first conductivity type arranged at the first side and between the first edge termination region and edge has a varying concentration of dopants of the first conductivity type which increases at least next to the first edge termination region substantially linearly with an increasing distance from the first edge termination region.