Abstract: A light-emitting device includes: a semiconductor stacked body including: an n-type semiconductor layer having an n-side contact surface, a light-emitting layer located on a region of the n-type semiconductor layer surrounding the n-side contact surface in a top-view, and a p-type semiconductor layer provided on the light-emitting layer; an n-side electrode contacting the n-side contact surface; a p-side electrode located on and contacting the p-type semiconductor layer; and an insulating film opposing a side surface of the light-emitting layer; wherein a first gap portion is located between the insulating film and the side surface of the light-emitting layer such that the side surface of the light-emitting layer is exposed at the first gap portion.

Abstract: Devices and methods for forming a device are presented. The device includes a substrate having a well of a first polarity type and a thyristor-based memory cell. The thyristor-based memory cell includes at least a first region of a second polarity type adjacent to the well, a gate which serves as a second word line disposed on the substrate, at least a first layer of the first polarity type disposed adjacent to the first region of the second polarity type and adjacent to the gate, and at least a heavily doped first layer of the second polarity type disposed on the first layer of the first polarity type and adjacent to the gate. At least the heavily doped first layer of the second polarity type is self-aligned with side of the gate.

Abstract: The present disclosure provides a semiconductor structure, including: a semiconductor device layer including a first surface and a second surface, wherein the first surface is at a front side of the semiconductor device layer, and the second surface is at a backside of the semiconductor device layer; an insulating layer above the second surface of the semiconductor device; and a through-silicon via (TSV) traversing the insulating layer. Associated manufacturing methods of the same are also provided.

Abstract: The present application discloses a display panel including a base substrate and a pixel-defining layer on a surface on the base substrate to define multiple subpixel regions arranged in multiple rows with each subpixel region surrounded by part of the pixel-defining layer. The pixel-defining layer includes one or more grooves. Each groove includes a container portion partially surrounded by an edge portion. The container portion is at a first height above the surface and the edge portion is at a second height greater than the first height relative to the surface. The edge portion of each groove includes one or more gaps to allow the container portion to connect to one or more subpixel regions respectively in one or two rows at one or both sides of the groove.

Abstract: Vertical GAA FET structures are disclosed in which a current-carrying nanowire is oriented substantially perpendicular to the surface of a silicon substrate. The vertical GAA FET is intended to meet design and performance criteria for the 7 nm technology generation. In some embodiments, electrical contacts to the drain and gate terminals of the vertically oriented GAA FET can be made via the backside of the substrate. Examples are disclosed in which various n-type and p-type transistor designs have different contact configurations. In one example, a backside gate contact extends through the isolation region between adjacent devices. Other embodiments feature dual gate contacts for circuit design flexibility. The different contact configurations can be used to adjust metal pattern density.

Abstract: An electronic device is based on a single crystal semiconductor substrate. A cavity is formed in the semiconductor substrate. Further, a movably suspended mass is defined by one or more trenches extending from one side of the semiconductor substrate to the cavity. A first electrode layer is provided on the suspended mass. Further, a cover layer covering the suspended mass is provided. The cover layer includes a second electrode layer arranged opposite to the first electrode layer and spaced therefrom by a gap.

Abstract: Discussed is an organic light emitting display device. The organic light emitting display device can include a first emission part, a second emission part on the first emission part, and a first P-type charge generation layer between the first emission part and the second emission part. The first emission part includes a first hole transport layer, a first emission layer, and a first electron transport layer. The second emission part includes a second hole transport layer, a second emission layer, and a second electron transport layer. The second hole transport layer and the first P-type charge generation layer are disposed adjacent to each other. The second hole transport layer includes a first material and a second material. The first material has an absolute value of a HOMO energy level which can be greater than an absolute value of a LUMO energy level of the first P-type charge generation layer.

Abstract: A method for manufacturing a semiconductor device includes forming a plurality of fins on a semiconductor substrate. In the method, sacrificial spacer layers are formed on the plurality of fins, and portions of the semiconductor substrate located under the sacrificial spacer layers and located at sides of the plurality of fins are removed. Bottom source/drain regions are grown in at least part of an area where the portions of the semiconductor substrate were removed, and sacrificial epitaxial layers are grown on the bottom source/drain regions. The method also includes diffusing dopants from the bottom source/drain regions and the sacrificial epitaxial layers into portions of the semiconductor substrate under the plurality of fins. The sacrificial epitaxial layers are removed, and bottom spacers are formed in at least part of an area where the sacrificial epitaxial layers were removed.

Abstract: A device includes an interposer, which includes a substrate having a top surface. An interconnect structure is formed over the top surface of the substrate, wherein the interconnect structure includes at least one dielectric layer, and metal features in the at least one dielectric layer. A plurality of through-substrate vias (TSVs) is in the substrate and electrically coupled to the interconnect structure. A first die is over and bonded onto the interposer. A second die is bonded onto the interposer, wherein the second die is under the interconnect structure.

Abstract: Aspects of the present invention relate to approaches for forming a semiconductor device such as a field-effect-transistor (FET) having a metal gate with improved performance. A metal gate is formed on a substrate in the semiconductor device. Further processing can result in unwanted oxidation in the metal that forms the metal gate. A reducing agent can be used to de-oxidize the metal that forms the metal gate, leaving a substantially non-oxidized surface.

Abstract: The present disclosure provides a bio-field effect transistor (BioFET) and a method of fabricating a BioFET device. The method includes forming a BioFET using one or more process steps compatible with or typical to a complementary metal-oxide-semiconductor (CMOS) process. The BioFET device includes a substrate, a transistor structure, an isolation layer, an interface layer in an opening of the isolation layer, and a metal crown structure over the interface layer. The interface layer and the metal crown structure are disposed on opposite side of the transistor from a gate structure.

Abstract: Embodiments of the disclosure include an electrostatic chuck assembly, a processing chamber and a method of maintaining a temperature of a substrate is provided. In one embodiment, an electrostatic chuck assembly is provided that includes an electrostatic chuck, a cooling plate and a gas box. The cooling plate includes a gas channel formed therein. The gas box is operable to control a flow of cooling gas through the gas channel.

Abstract: A method for producing a semiconductor power device, includes forming a gate trench from a surface of a semiconductor layer toward an inside thereof. A first insulation film is formed on an inner surface of the gate trench. The method also includes removing a part on a bottom surface of the gate trench in the first insulation film. A second insulation film having a dielectric constant higher than SiO2 is formed in such a way as to cover the bottom surface of the gate trench exposed by removing the first insulation film.

Abstract: The present specification relates to an organic light emitting diode.

Abstract: A semiconductor device including semiconductor material having a bend and a trench feature formed at the bend, and a gate structure at least partially disposed in the trench feature. A method of fabricating a semiconductor structure including forming a semiconductor material with a trench feature over a layer, forming a gate structure at least partially in the trench feature, and bending the semiconductor material such that stress is induced in the semiconductor material in an inversion channel region of the gate structure.

Abstract: Package structures and methods for forming the same are provided. The method includes providing a first integrated circuit die and forming a redistribution structure over the first integrated circuit die. The method also includes forming a base layer over the redistribution structure. The base layer has first and second openings. The first openings are wider than the second openings. The method further includes forming first bumps over the redistribution structure. The first bumps have a lower portion filling the first openings. In addition, the method includes bonding a second integrated circuit die to the redistribution structure through second bumps having a lower portion filling the second openings. There is a space between the second integrated circuit die and the base layer. The method also includes forming a molding compound layer over the base layer. The molding compound layer fills the space and surrounds the first and second bumps.

Abstract: A flexible display assembly, a manufacturing method thereof, and a display panel are provided. The flexible display assembly comprises a display layer, a first thin film layer, and a second thin film layer. The display layer comprises a non-bending region and a bending region. The first thin film layer comprises at least a first inorganic layer and organic layer formed sequentially in the bending region. The second thin film layer comprises and a second inorganic layer and organic layer formed sequentially in the non-bending region. A modulus difference between the first inorganic layer and the display layer is less than that between the second inorganic layer and the display layer, and/or a thickness of the first inorganic layer is less than that of the second inorganic layer; a thickness of the first thin film layer is equal to that of the second thin film layer.

Abstract: A silicon carbide semiconductor device, including a silicon carbide semiconductor substrate of a first conductivity type, a first silicon carbide semiconductor deposition layer of the first conductivity type, deposited on a front surface of the silicon carbide semiconductor substrate and having an impurity concentration that is lower than that of the silicon carbide semiconductor substrate, a base region of a second conductivity type, selectively provided in the first silicon carbide semiconductor deposition layer at a front surface thereof, and a second silicon carbide semiconductor deposition layer of the second conductivity type, deposited on the front surface of the first silicon carbide semiconductor deposition layer. The base region has an impurity concentration of 1×1018 to 1×1020/cm3 and a thickness of 0.3 to 1.0 ?m. The second silicon carbide semiconductor deposition layer has a surface defect density of 3 defects/cm2.

Abstract: An object is to provide a semiconductor device including an oxide semiconductor with stable electric characteristics can be provided. An insulating layer having many defects typified by dangling bonds is formed over an oxide semiconductor layer with an oxygen-excess mixed region or an oxygen-excess oxide insulating layer interposed therebetween, whereby impurities in the oxide semiconductor layer, such as hydrogen or moisture (a hydrogen atom or a compound including a hydrogen atom such as H2O), are moved through the oxygen-excess mixed region or oxygen-excess oxide insulating layer and diffused into the insulating layer. Thus, the impurity concentration of the oxide semiconductor layer is reduced.

Abstract: A display panel and a method for fabricating the same are provided. The display panel includes: a TFT array substrate; an OLED array disposed on the TFT array substrate, a package layer which covers the OLED array, an upper protection layer covering the package layer, and a lower protection layer. In a first direction, a first projection of the OLED array on the TFT array substrate is located within a second projection of the package layer on the TFT array substrate, and there is a first distance between a boundary of the first projection and a boundary of the second projection. Also in the first direction, the second projection is located within a third projection of the upper protection layer on the TFT array substrate, and there is a second distance between the boundary of the second projection and a boundary of the third projection.