Abstract: The present invention relates to a Field-Effect Transistor (FET) and, more particularly, to a Dielectric-Modulated Field-Effect Transistor (DMFET) and a method of fabricating the same. A DMFET according to an embodiment of the present invention comprises a substrate in which a source and a drain are formed, wherein the source and the drain are spaced apart from each other, a gate formed on a region between the source and the drain, of the substrate, wherein at least part of the gate is spaced apart from the substrate, biomolecules formed below a region spaced apart from the substrate, of the gate, and a linker for combining the gate and the biomolecules.

Abstract: A method for manufacturing a semiconductor device includes: (a) transferring an electronic component that has an electrode and formed on a first substrate from the first substrate to a second substrate; and (b) forming a wiring line electrically coupling the electrode and a terminal on the second substrate. A cavity is provided between the electrode of the electronic component transferred on the second substrate and the second substrate, and the wiring line is formed in the cavity.

Abstract: The present invention relates to a transistor in a semiconductor device and method of manufacturing the same. Trenches are formed in a semiconductor substrate at gate edges. Low-concentration impurity regions are then formed at the sidewalls and the bottoms of the trenches. High-concentration impurity regions are formed at the bottoms of the trenches in a depth shallower than the low-concentration impurity regions. Source/drain consisting of the low-concentration impurity regions and the high-concentration impurity regions are thus formed. Therefore, the size of the transistor can be reduced while securing a stabilized operating characteristic even at high voltage. It is thus possible to improve reliability of the circuit and the degree of integration in the device.

Abstract: An electroluminescence (EL) device includes a substrate and a plurality of pixels formed on the substrate. Each pixel includes a first area including at least a first capacitor and a second capacitor, the first capacitor including a first conductive layer, a first dielectric layer over the first conductive layer, and a second conductive layer over the first dielectric layer, and the second capacitor including the second conductive layer, a second dielectric layer over the second conductive layer, and a third conductive layer over the second dielectric layer, and a second area including a first semiconductor layer formed on the substrate, a first gate oxide layer over the first semiconductor layer, and a fourth conductive layer over the first gate oxide layer.

Abstract: A semiconductor device is fabricated to include source and drain contacts including an ohmic metal sunken into the barrier layer and a portion of the channel layer; a protective dielectric layer disposed between the source and drain contacts on the barrier layer; a metallization layer disposed in drain and source ohmic vias between the source contact and the protective dielectric layer and between the protective dielectric layer and the drain contact; and a metal T-gate disposed above the barrier layer including a field mitigating plate disposed on a side portion of a stem of the metal T-gate.

Abstract: An LED includes a circuit board (1), a light emitter (3) mounted on the circuit board (1), and a reflector (4) mounted on the circuit board (1), the light emitter (3) including an LED element mounted on the circuit board (1) and a light-transmitting resin (2) to seal the LED element. The reflector (4) is configured to surround the light emitter (3) and includes an opening (5) which passes through an upper surface and a lower surface is provided at a central position to allow insertion of the light emitter (3), and an inclined inner surface in the opening (6) configured to be upwardly broadened. A reflection film (7) is provided on the inclined inner surface (6) of the opening in the reflector. A outer peripheral edge is a non-reflection film constituted area (8) and, simultaneously, a terminal position identification mark (10) adjacent to the non-reflection film constituted area (8) are provided.

Abstract: A photodiode array 1 is provided with an n-type silicon substrate 3. A plurality of photodiodes 4 are formed in array on the opposites surface side to an incident surface of light L to be detected, in the n-type silicon substrate 3. A depression 6 with a predetermined depth more depressed than a region not corresponding to regions where the photodiodes 4 are formed is formed in regions corresponding to the regions where the photodiodes 4 are formed, on the incident surface side of the light L to be detected, in the n-type silicon substrate 3.

Abstract: A method for fabricating a non-volatile memory is provided. The method includes a stacked structure and a consuming layer are formed in sequence over a substrate. A converting process is performed at a peripheral region of the consuming layer to form a first insulating layer. A conductive layer is formed over the stacked layer and the first insulating layer.

Abstract: Semiconductor component including a drift region and a drift control region. One embodiment provides a drift zone and a drift control zone. A drift control zone dielectric is arranged between the first drift zone and the drift control zone and has at least two sections arranged at a distance from one another in a current flow direction of the component. At least one separating structure is arranged between the drift zone and the drift control zone in the region of an interruption, defined by the at least two sections, of the drift control zone dielectric and has at least one PN junction.

Abstract: A semiconductor device includes a first active pattern protruding from a substrate, a second active pattern on the first active pattern, a gate electrode enclosing a sidewall of the second active pattern, a conductive layer pattern on the first active pattern, a first impurity region in the first active pattern, and a second impurity region at a surface portion of the second active pattern. The first active pattern extending along a predetermined direction may have a first region and a second region. The second active pattern may have a pillar structure and the conductive layer pattern may include a metal or a metal compound.

Abstract: A semiconductor device includes plural fuse elements which can be disconnected by irradiating a laser beam, and attenuation members which are located between the plural fuse elements as viewed two-dimensionally and can attenuate the laser beam. Each attenuation member includes plural columnar bodies. With this arrangement, the attenuation members including plural columnar units absorb the laser beam leaked out from a fuse element to be disconnected to a semiconductor substrate side. The laser beam is also scattered by Fresnel diffraction. Therefore, the columnar body can efficiently attenuate the laser beam, without generating a crack in the insulation film by absorbing excessive energy.

Abstract: A complementary semiconductor device includes a semiconductor substrate, a first semiconductor region formed on a surface of the semiconductor substrate, a second semiconductor region formed on the surface of the semiconductor substrate apart from the first semiconductor region, an n-MIS transistor having a first gate insulating film including La and Al, formed on the first semiconductor region, and a first gate electrode formed on the gate insulating film, and a p-MIS transistor having a second gate insulating film including La and Al, formed on the second semiconductor region, and a second gate electrode formed on the gate insulating film, an atomic density ratio Al/La in the second gate insulating film being larger than an atomic density ratio Al/La in the first gate insulating film.

Abstract: A semiconductor substrate has a second conductivity type cathode layer formed thereon. The cathode layer has a first conductivity type base layer formed thereon. A first anode region of the second conductivity type is formed in the surface of the base layer. A second anode region of the first conductivity type is formed in the first anode region. A first semiconductor region of the first conductivity type is formed in contact with the semiconductor substrate. A second semiconductor region of the second conductivity type is formed adjacent to the first semiconductor region and in contact with the cathode layer. An intermediate electrode is formed on the surfaces of the first semiconductor region and the contact region.

Abstract: In an embodiment, a memory device, including: a semiconductor fin structure, each end portion of the fin structure including a source/drain region; a charge storage layer covering at least a portion of the fin structure; and a gate layer covering at least a portion of the charge storage layer.

Abstract: Provided is a method for fabricating a transistor in a semiconductor device. The method includes forming an etch stop layer pattern over a semiconductor substrate; forming a semiconductor layer for covering the etch stop layer pattern; forming a recess trench that exposes an upper surface of the etch stop layer pattern by etching the semiconductor layer pattern; removing the etch stop layer pattern exposed in the recess trench; and forming a gate that fills the recess trench.

Abstract: A method for fabricating a semiconductor device, the method includes forming an isolation layer defining an active region over a substrate, forming a conductive layer over the substrate including the isolation layer, patterning the conductive layer to form a conductive pattern over the active region defined on both sides of a gate region, forming insulation spacers on a sidewall of the conductive pattern, forming a conductive layer for a gate electrode and a gate hard mask layer over the resulting structure including the conductive pattern, and patterning the gate hard mask layer and the conductive layer for the gate electrode to form a gate in the gate region of the substrate.

Abstract: A semiconductor device is fabricated having a stack gate structure where a first gate electrode, a second gate electrode and a gate hard mask are stacked. The stack gate structure secures a contact open margin while reducing a loss of the gate hard mask during a self-aligned contact (SAC) etching process of forming a landing plug contact. An intermediate connection layer is formed in a landing plug contact region between the first gate electrodes. Furthermore, the occurrence of a bridge between a gate and a contact can be prevented while forming the landing plug contact. A conductive material is filled into a gate region including a recess between intermediate connection layers to form the first gate electrode. The second gate electrode and the gate hard mask are formed during a gate-patterning process using a gate mask, even though misalignment occurs between the gate and the contact.

Abstract: A memory cell that includes a control gate disposed laterally between two floating gates where each floating gate is capable of holding data. Each floating gate in a memory cell may be erased and programmed by applying a combination of voltages to diffusion regions, the control gate, and a well. A plurality of memory cells creates a memory string, and a memory array is formed from a plurality of memory strings arranged in rows and columns.

Abstract: A semiconductor device including semiconductor material having a bend and a trench feature formed at the bend, and a gate structure at least partially disposed in the trench feature. A method of fabricating a semiconductor structure including forming a semiconductor material with a trench feature over a layer, forming a gate structure at least partially in the trench feature, and bending the semiconductor material such that stress is induced in the semiconductor material in an inversion channel region of the gate structure.

Abstract: An image sensor device includes an optical black pixel region and an active pixel region. The image sensor device includes a light receiving unit including a plurality of light sensitive semiconductor devices that are configured to detect light incident thereon, a pixel metal wire layer including a transparent material on the light receiving unit and including a plurality of metal wires therein, and a filter unit on the pixel metal wire layer. The filter unit includes a plurality of filters that are configured to transmit light according to a wavelength thereof. The filters of the filter unit in the optical black pixel region of the image sensor device have a single color. The image sensor device further includes a light blocking layer in the optical black pixel region between the filter unit and the light receiving unit. The light blocking layer is configured to block light that passes through the filter unit.