Abstract: A method of manufacturing a non-volatile memory is described. A substrate including a first region and a second region located at periphery of the first region is provided. A plurality of stacked structures are formed on the first region of the substrate. A wall structure is formed on the second region of the substrate. A conductive layer is formed over the substrate. A bottom anti-reflective coating is formed over the conductive layer. The bottom anti-reflective coating and the conductive layer are etched back. The conductive layer is patterned.

Abstract: A method for forming a micro-electro mechanical system (MEMS) device is provided. The method includes forming a first dielectric layer over a semiconductor layer and forming a blocking layer over the first dielectric layer. The method also includes bonding a CMOS substrate with the blocking layer, and the CMOS substrate includes a second dielectric layer, and the blocking layer is configured to block gas coming from the second dielectric layer. The method further includes partially removing the first dielectric layer to form a cavity between the semiconductor layer and the blocking layer. A portion of the semiconductor layer above the cavity becomes a movable element. In addition, the method includes sealing the cavity such that a closed chamber is formed to surround the movable element.

Abstract: Disclosed is an organic light emitting display device that may include an anode electrode; an organic emitting layer on the anode electrode; a cathode electrode on the organic emitting layer; an auxiliary electrode electrically connected with the cathode electrode; and a contact electrode that is on a same layer as the auxiliary electrode, the contact electrode horizontally spaced apart from the auxiliary electrode, the contact electrode directly connected with both the auxiliary electrode and the cathode electrode to connect together the auxiliary electrode and a portion of the cathode electrode that is on a same layer as the auxiliary electrode.

Abstract: A bidirectional Zener diode includes a substrate. A first conductivity type base region is formed in a surficial portion of the substrate. A second conductivity type first impurity region is formed in a surficial portion of the base region so as to form a pn junction with the base region. A second conductivity type second impurity region is formed in a surficial portion of the base region in a manner spaced apart from the first impurity region so as to form a pn junction with the base region. A first electrode is arranged at the surface of the substrate. A second electrode is arranged at the surface of the substrate. A dimension of the base region along the surface of the substrate between the first impurity region and the second impurity region is equal to or greater than 4.0 ?m and equal to or smaller than 12.5 ?m.

Abstract: The invention relates to a radiation-emitting device (600), which comprises a substrate (100), an inner optoelectronic component (300) and an outer optoelectronic component (200) which at least partially laterally surrounds the inner optoelectronic component (300). Further, the radiation-emitting device (600) has a cover element (500) which is arranged on the optoelectronic components (200, 300) and comprises a first contact element (521), connected to a first electrode surface of the inner optoelectronic component (300) in an electrically conductive manner, and a second contact element (522) connected to a second electrode surface of the inner optoelectronic component (300) in an electrically conductive manner.

Abstract: A method for manufacturing a microelectromechanical systems (MEMS) device is provided. According to some embodiments of the method, a semiconductor structure is provided. The semiconductor structure includes an integrated circuit (IC) substrate, a dielectric layer arranged over the IC substrate, and a MEMS substrate arranged over the IC substrate and the dielectric layer to define a cavity between the MEMS substrate and the IC substrate. The MEMS substrate includes a MEMS hole in fluid communication with the cavity and extending through the MEMS substrate. A sealing layer is formed over or lining the MEMS hole to hermetically seal the cavity with a reference pressure while the semiconductor structure is arranged within a vacuum having the reference pressure. The semiconductor structure resulting from application of the method is also provided.

Abstract: A method for producing an integrated circuit pointed element is disclosed. An element has a projection with a concave part directing its concavity towards the element. The element includes a first etchable material. A zone is formed around the concave part of the element. The zone includes a second material that is less rapidly etchable than the first material for a particular etchant. The first material and the second material are etched with the particular etchant to form an open crater in the concave part and thus to form a pointed region of the element.

Abstract: A device includes an interposer, which includes a substrate having a top surface. An interconnect structure is formed over the top surface of the substrate, wherein the interconnect structure includes at least one dielectric layer, and metal features in the at least one dielectric layer. A plurality of through-substrate vias (TSVs) is in the substrate and electrically coupled to the interconnect structure. A first die is over and bonded onto the interposer. A second die is bonded onto the interposer, wherein the second die is under the interconnect structure.

Abstract: A display device according to an exemplary embodiment of the present inventive concept includes: a first insulation substrate; a thin film transistor disposed on the first insulation substrate; a pixel electrode coupled to the thin film transistor; a second insulation substrate facing the first insulation substrate; and a common electrode disposed on the second insulation substrate. The pixel electrode includes a first subpixel electrode including a first vertical stem portion and a first horizontal stem portion that is disposed perpendicular to the first vertical stem portion at an end of the first vertical stem portion, and a second subpixel electrode including a second vertical stem portion and a second horizontal stem portion that is disposed perpendicular to the second vertical stem portion at an end of the second vertical step portion.

Abstract: An image sensor may include a symmetrical imaging pixel with a floating diffusion region. The floating diffusion region may be formed in the center of the imaging pixel. A shallow p-well may be formed around the floating diffusion region. A transfer gate configured to transfer charge from a photodiode to the floating diffusion region may be ring-shaped with an opening that overlaps the floating diffusion region. Isolation regions including deep trench isolation and a p-well may surround the photodiode of the imaging pixel. A p-stripe may couple the shallow p-well around the floating diffusion region to the isolation regions. The floating diffusion regions of neighboring pixels may be coupled together with additional conductive layers to implement shared configurations.

Abstract: An organic light-emitting diode (OLED) display and a method of manufacturing the same are disclosed. In one aspect, the display includes a lower substrate with a display area and a peripheral area surrounding the display area, an upper substrate facing the lower substrate and a display unit disposed on the display area. The display also includes a sealant disposed on the peripheral area and sealing the lower and upper substrates and a first metal layer interposed between the lower substrate and the sealant. The first metal layer includes a plurality of first through-portions extending in a first direction and arranged in a second direction crossing the first direction. The display also includes a second metal layer disposed on the first metal layer and comprising a plurality of second through-portions respectively corresponding to the first through-portions.

Abstract: A conductive feature on a semiconductor component is disclosed. A first passivation layer is formed over a substrate. A bond pad is formed over the first passivation layer. A second passivation layer overlies the first passivation layer and the bond pad. The second passivation layer has a first opening overlying the bond pad and a plurality of second openings exposing a top surface of the first passivation layer. A buffer layer overlies the second passivation layer and fills the plurality of second openings. The buffer layer has a third opening overlapping the first opening and together exposes a portion the bond pad. The combined first opening and third opening has sidewalls. An under bump metallurgy (UBM) layer overlies the sidewalls of the combined first opening and third opening, and contacts the exposed portion of the bond pad. A conductive feature overlies the UBM layer.

Abstract: Disclosed is an organic light emitting display device that may include an anode electrode; an organic emitting layer on the anode electrode; a cathode electrode on the organic emitting layer; an auxiliary electrode electrically connected with the cathode electrode; and a contact electrode that is on a same layer as the auxiliary electrode, the contact electrode horizontally spaced apart from the auxiliary electrode, the contact electrode directly connected with both the auxiliary electrode and the cathode electrode to connect together the auxiliary electrode and a portion of the cathode electrode that is on a same layer as the auxiliary electrode.

Abstract: A semiconductor device includes a plurality of wire bonds formed on a surface of the semiconductor device by bonding each of a plurality of copper wires onto corresponding ones of a plurality of aluminum pads; a protective material is applied around the plurality of wire bonds, the protective material having a first pH; and at least a portion of the semiconductor device and the protective material are encapsulated with an encapsulating material having a second pH, wherein the first pH of the protective material is for neutralizing the second pH of the encapsulating material around the plurality of wire bonds.

Abstract: A semiconductor device including drivers is disclosed, which can maximize driving ability of a plurality of drivers installed in a given region when the plurality of drivers is arranged in an array shape. The semiconductor device includes: a first active region; a second active region spaced apart from the first active region a predetermined distance in a first direction; a first gate finger group located in the first active region, and configured to include an odd number of gate fingers; and a second gate finger group located in the second active region, and configured to include an even number of gate fingers electrically coupled to the gate fingers of the first gate finger group.

Abstract: The present invention relates to a process of making a zinc-oxide-based thin film semiconductor, for use in a transistor, comprising thin film deposition onto a substrate comprising providing a plurality of gaseous materials comprising at least first, second, and third gaseous materials, wherein the first gaseous material is a zinc-containing volatile material and the second gaseous material is reactive therewith such that when one of the first or second gaseous materials are on the surface of the substrate the other of the first or second gaseous materials will react to deposit a layer of material on the substrate and wherein the third gaseous material is inert with respect to reacting with the first or second gaseous materials.

Abstract: Methods and a structure. A method of forming contact structure includes depositing a silicide layer onto a substrate; depositing an electrically insulating layer over a first surface of the silicide layer; forming a via through the insulating layer extending to the first surface; depositing an electrically conductive layer covering a bottom and at least one vertical wall of the via; removing the conductive layer from the bottom; and filling the via with aluminum directly contacting the silicide layer. A structure includes: a silicide layer disposed on a substrate; an electrically insulating layer disposed over the silicide layer; an aluminum plug extending through the insulating layer and directly contacting the silicide layer; and an electrically conductive layer disposed between the plug and the insulating layer. Also included is a method where an aluminum layer grows selectively from a silicide layer and at least one sidewall of a trench.

Abstract: Provided is a method of manufacturing a semiconductor device including: arranging multiple dies planarly between a first lead frame plate and a second lead frame plate, which face each other, to connect the multiple semiconductor chips to each of the first lead frame plate and the second lead frame plate; filling a resin between the first lead frame plate and the second lead frame plate to seal the multiple dies; performing a first dicing on a laminated body including the first lead frame plate, the resin, and the second lead frame plate, between the adjacent dies, to separate at least the first lead frame plate by cutting; applying plating to the laminated body with at least the first lead frame plate being separated by cutting; and performing a second dicing on a remainder of the laminated body between the adjacent dies, to separate the laminated body into individual semiconductor devices.

Abstract: A semiconductor photodetector device (PD1) comprises a multilayer structure (LS1) and a glass substrate (1) optically transparent to incident light. The multilayer structure includes an etching stop layer (2), an n-type high-concentration carrier layer (3), an n-type light-absorbing layer (5), and an n-type cap layer (7) which are laminated. A photodetecting region (9) is formed near a first main face (101) of the multilayer structure, whereas a first electrode (21) is provided on the first main face. A second electrode (27) and a third electrode (31) are provided on a second main face (102). A film (10) covering the photodetecting region and first electrode is formed on the first main face. A glass substrate (1) is secured to the front face (10a) of this film.

Abstract: Described is a CMOS transistor structure with a multi-layered gate electrode structure and a method of fabrication. The gate electrode structure has a three-layered metallic gate electrode and a polysilicon layer. The first metallic layer acts as a barrier to prevent the second metallic layer from reacting with an underlying dielectric. The second metallic layer acts to set the work function of the gate electrode structure. The third metallic layer acts as a barrier to prevent the second metallic layer from reacting with the polysilicon layer.