Patents Examined by Anita K Alanko
  • Alternating self-assembling morphologies of diblock copolymers controlled by variations in surfaces
    Patent number: 8404124
    Abstract: Methods for fabricating sublithographic, nanoscale microstructures arrays including openings and linear microchannels utilizing self-assembling block copolymers, and films and devices formed from these methods are provided. In some embodiments, the films can be used as a template or mask to etch openings in an underlying material layer.
    Type: Grant
    Filed: June 12, 2007
    Date of Patent: March 26, 2013
    Assignee: Micron Technology, Inc.
    Inventors: Dan B. Millward, Donald Westmoreland, Gurtej Sandhu
  • Alternating self-assembling morphologies of diblock copolymers controlled by variations in surfaces
    Patent number: 8123962
    Abstract: Methods for fabricating sublithographic, nanoscale microstructures arrays including openings and linear microchannels utilizing self-assembling block copolymers, and films and devices formed from these methods are provided. In some embodiments, the films can be used as a template or mask to etch openings in an underlying material layer.
    Type: Grant
    Filed: June 12, 2007
    Date of Patent: February 28, 2012
    Assignee: Micron Technology, Inc.
    Inventors: Dan B. Millward, Donald Westmoreland, Gurtej Sandhu
  • Sub-10 nm line features via rapid graphoepitaxial self-assembly of amphiphilic monolayers
    Patent number: 8123960
    Abstract: Methods for fabricating sublithographic, nanoscale microchannels utilizing an aqueous emulsion of an amphiphilic agent and a water-soluble, hydrogel-forming polymer, and films and devices formed from these methods are provided.
    Type: Grant
    Filed: March 22, 2007
    Date of Patent: February 28, 2012
    Assignee: Micron Technology, Inc.
    Inventor: Dan B. Millward
  • Multi-layer method for formation of registered arrays of cylindrical pores in polymer films
    Patent number: 8114300
    Abstract: Methods for fabricating sublithographic, nanoscale polymeric microstructures utilizing self-assembling block copolymers, and films and devices formed from these methods are provided.
    Type: Grant
    Filed: April 21, 2008
    Date of Patent: February 14, 2012
    Assignee: Micron Technology, Inc.
    Inventor: Dan B. Millward
  • Graphoepitaxial self-assembly of arrays of downward facing half-cylinders
    Patent number: 8114301
    Abstract: Methods for fabricating sublithographic, nanoscale microstructures in line arrays utilizing self-assembling block copolymers, and films and devices formed from these methods are provided.
    Type: Grant
    Filed: May 2, 2008
    Date of Patent: February 14, 2012
    Assignee: Micron Technology, Inc.
    Inventors: Dan B. Millward, Donald Westmoreland
  • Registered structure formation via the application of directed thermal energy to diblock copolymer films
    Patent number: 8083953
    Abstract: Methods for fabricating sublithographic, nanoscale linear microchannel arrays over surfaces without defined features utilizing self-assembling block copolymers, and films and devices formed from these methods are provided. Embodiments of the methods use a multilayer induced ordering approach to align lamellar films to an underlying base film within trenches, and localized heating to anneal the lamellar-phase block copolymer film overlying the trenches and outwardly over the remaining surface.
    Type: Grant
    Filed: March 6, 2007
    Date of Patent: December 27, 2011
    Assignee: Micron Technology, Inc.
    Inventors: Dan B. Millward, Eugene P. Marsh
  • Patterning by energetically-stimulated local removal of solid-condensed-gas layers and solid state chemical reactions produced with such layers
    Patent number: 7993538
    Abstract: The invention provides a method for forming a patterned material layer on a structure, by condensing a vapor to a solid condensate layer on a surface of the structure and then localized removal of selected regions of the condensate layer by directing a beam of energy at the selected regions. The structure can then be processed, with at least a portion of the patterned solid condensate layer on the structure surface, and then the solid condensate layer removed. Further there can be stimulated localized reaction between the solid condensate layer and the structure by directing a beam of energy at at least one selected region of the condensate layer.
    Type: Grant
    Filed: October 10, 2008
    Date of Patent: August 9, 2011
    Assignee: President and Fellows of Harvard College
    Inventors: Jene A. Golovchenko, Gavin M. King, Gregor M. Schurmann, Daniel Branton
  • Semiconductor manufacturing process
    Patent number: 7977244
    Abstract: Disclosed is a semiconductor manufacturing process, in which a fluorine radical-containing plasma is used to etch a hard mask and a layer therebeneath; and a treatment is carried out using a gas reactive to fluorine radicals for reacting with residual fluorine radicals to form a fluorine-containing compound and remove it. Thus, precipitates formed by the reaction of fluorine radicals and titanium components existing in the hard mask to cause a process defect can be avoided.
    Type: Grant
    Filed: December 18, 2006
    Date of Patent: July 12, 2011
    Assignee: United Microelectronics Corp.
    Inventors: Yu-Tsung Lai, Chun-Jen Huang, Jyh-Cherng Yau, Jiunn-Hsiung Liao
  • Method of making reliable wafer level chip scale package semiconductor devices
    Patent number: 7972521
    Abstract: The present invention relates to a method of making a robust wafer level chip scale package and, in particular, a method that prevents cracking of the passivation layer during solder flow and subsequent multiple thermal reflow steps. In one embodiment, a passivation layer that is formed using an insulating material applied in a highly compressive manner is used. In another aspect, another layer is applied over the passivation layer to assist with preventing cracking of the passivation layer.
    Type: Grant
    Filed: March 12, 2007
    Date of Patent: July 5, 2011
    Assignee: Semiconductor Components Industries LLC
    Inventors: Umesh Sharma, Harry Yue Gee, Phillip Gene Holland
  • Methods using block copolymer self-assembly for sub-lithographic patterning
    Patent number: 7964107
    Abstract: Block copolymers can be self-assembled and used in methods as described herein for sub-lithographic patterning, for example. The block copolymers can be diblock copolymers, triblock copolymers, multiblock copolymers, or combinations thereof. Such methods can be useful for making devices that include, for example, sub-lithographic conductive lines.
    Type: Grant
    Filed: February 8, 2007
    Date of Patent: June 21, 2011
    Assignee: Micron Technology, Inc.
    Inventor: Dan B. Millward
  • Medical devices having textured surfaces
    Patent number: 7955512
    Abstract: Disclosed are medical devices having textured surfaces and related methods for texturing. Methods of surface texturing using gas-phase plasma provide medical devices with myriad complex surface morphologies.
    Type: Grant
    Filed: February 13, 2007
    Date of Patent: June 7, 2011
    Assignee: Medtronic, Inc.
    Inventors: Eunsung Park, Catherine E. Taylor, Kevin Casey
  • Manufacturing method of liquid discharge head and orifice plate
    Patent number: 7955509
    Abstract: There is disclosed a manufacturing method in which depths of individual liquid chambers can be set to be small. The manufacturing method is a manufacturing method of a liquid discharge head having a liquid chamber which communicates with a discharge port for discharging a liquid, and includes: etching a first Si layer of an SOI substrate by use of an insulating layer as an etching stop layer to form the liquid chamber at the first Si layer, the SOI substrate being constituted by the first Si layer, the insulating layer and a second Si layer in this order; and removing a part or all of the second Si layer.
    Type: Grant
    Filed: September 14, 2007
    Date of Patent: June 7, 2011
    Assignee: Canon Kabushiki Kaisha
    Inventor: Satoshi Nozu
  • Method of manufacturing piezoelectric resonator
    Patent number: 7947187
    Abstract: When forming an opening conforming to a groove of a quartz resonator in a metal film serving as a mask of the quartz resonator by conducting etching, the outer periphery of the metal film is wavingly etched. Therefore, when the groove is formed on the quartz resonator, the quartz resonator is formed according to the above-described metal film, which results in appearance defects or dimension defects. In order to solve the problems, the outer shape of the metal film is formed smaller than the outer shape of the quartz resonator before forming the opening conforming to the groove of the quartz resonator in the metal film, then etching of the metal film and etching of the quartz resonator are performed.
    Type: Grant
    Filed: September 18, 2007
    Date of Patent: May 24, 2011
    Assignee: Nihon Dempa Kogyo Co., Ltd.
    Inventor: Takefumi Saito
  • Method for pattern formation
    Patent number: 7931819
    Abstract: There is provided a method for pattern formation, including a step of coating a composition comprising a block copolymer, a silicon compound, and a solvent for dissolving these components onto an object to form a layer of the composition on the object, a step of subjecting the layer of the composition to self-organization of the block copolymer to cause phase separation into a first phase, in which the silicon compound is localized, having higher etching resistance by heat treatment or/and oxygen plasma treatment, and a second phase comprising a polymer phase and having lower etching resistance by heat treatment or/and oxygen plasma treatment, and thereby forming a pattern layer with a fine pattern, and a step of etching the object using as a mask the thus formed pattern layer.
    Type: Grant
    Filed: March 23, 2007
    Date of Patent: April 26, 2011
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Naoko Kihara, Hiroyuki Hieda
  • Method and device for removing layers in some areas of glass plates
    Patent number: 7922925
    Abstract: Substrates with a coating, in particular a metal-containing coating, are freed of coating in some regions, in particular in the edge region, with the aid of plasma directed onto the coated side of the substrate. The width of the region in which the coating is removed may be set such that plasma from a number of plasma heads arranged next to one another in a row or from one plasma head with variable cross section is directed onto the substrate in the desired width from which the coating is to be removed, wherein the plasma head or heads is/are suitably aligned with respect to the substrate and/or the required number of plasma heads in each case are set in operation. It is also possible to remove coatings only partially in terms of the layer thickness.
    Type: Grant
    Filed: June 16, 2004
    Date of Patent: April 12, 2011
    Assignee: Saint-Gobain Glass France
    Inventors: Helmut Forstner, Alfred Hofrichter
  • Plasma reactor control by translating desired values of M plasma parameters to values of N chamber parameters
    Patent number: 7901952
    Abstract: The invention concerns a method of processing a wafer in a plasma reactor chamber by controlling plural chamber parameters in accordance with desired values of plural plasma parameters. The method includes concurrently translating a set of M desired values for M plasma parameters to a set of N values for respective N chamber parameters. The M plasma parameters are selected from a group including wafer voltage, ion density, etch rate, wafer current, etch selectivity, ion energy and ion mass. The N chamber parameters are selected from a group including source power, bias power, chamber pressure, inner magnet coil current, outer magnet coil current, inner zone gas flow rate, outer zone gas flow rate, inner zone gas composition, outer zone gas composition. The method further includes setting the N chamber parameters to the set of N values.
    Type: Grant
    Filed: December 11, 2006
    Date of Patent: March 8, 2011
    Assignee: Applied Materials, Inc.
    Inventors: Daniel J. Hoffman, Ezra Robert Gold
  • Apparatus for etching or stripping substrate of liquid crystal display device and method thereof
    Patent number: 7897056
    Abstract: Disclosed are an apparatus for etching or stripping a substrate of a liquid crystal display device and a method thereof. The present invention includes carrying out an etching or stripping process on substrates using an etchant in a first etchant tank, counting a number of the substrates etched or stripped using the etchant in the first etchant tank, checking readiness of a second etchant tank at a predetermined point in time before the counted number reaches a maximum substrate number set up previously for the etchant tanks, and carrying out the etching or stripping process on the substrates using an etchant in the second etchant tank when the second etchant tank is in readiness for use and the counted number reaches the maximum substrate number.
    Type: Grant
    Filed: October 18, 2002
    Date of Patent: March 1, 2011
    Assignee: LG Display Co., Ltd.
    Inventors: Won Jae Lee, Dug Jang Lee
  • Use of ultra-high magnetic fields in resputter and plasma etching
    Patent number: 7897516
    Abstract: Methods for resputtering and plasma etching include an operation of generating an ultra-high density plasma using an ultra-high magnetic field. For example, a plasma density of at least about 1013 electrons/cm3 is achieved by confining a plasma using a magnetic field of at least about 1 Tesla. The ultra-high density plasma is used to create a high flux of low energy ions at the wafer surface. The formed high density low energy plasma can be used to sputter etch a diffusion barrier or a seed layer material in the presence of an exposed low-k dielectric layer. For example, a diffusion barrier material can be etched with a high etch rate to deposition rate (E/D) ratio (e.g., with E/D>2) without substantially damaging an exposed dielectric layer. Resputtering and plasma etching can be performed, for example, in iPVD and in plasma pre-clean tools, equipped with magnets configured for confining a plasma.
    Type: Grant
    Filed: May 24, 2007
    Date of Patent: March 1, 2011
    Assignee: Novellus Systems, Inc.
    Inventors: Ronald L. Kinder, Anshu A. Pradhan
  • Sensor for detection of gas such as hydrogen and method of fabrication
    Patent number: 7897057
    Abstract: A gas sensor system and its method of fabrication is disclosed. The sensor system comprises an optrode, light source, and a light detector. In a sensor for hydrogen gas, the optrode is comprised of a porous substrate into which an intimate mixture of reagent and catalyst is incorporated. The mixture reacts with the hydrogen to produce a color/intensity change in relation to the concentration of gas. The optrode further includes a reversing agent, boron, to restore the benchmark conditions of the sensor system in real-time. The method of fabricating the optrode includes the steps of cleaning; etching to achieve the proper porosity; incorporating the reagent, catalyst, and reversing agent using capillary action; and removing excess reagent and catalyst.
    Type: Grant
    Filed: February 28, 2007
    Date of Patent: March 1, 2011
    Assignee: Optech Ventures, LLC
    Inventors: Paul B. O'Connor, Kisholoy Goswam
  • Wet etching process
    Patent number: 7892440
    Abstract: The present invention illustrates a bulk silicon etching technique that yields straight sidewalls, through wafer structures in very short times using standard silicon wet etching techniques. The method of the present invention employs selective porous silicon formation and dissolution to create high aspect ratio structures with straight sidewalls for through wafer MEMS processing.
    Type: Grant
    Filed: July 26, 2007
    Date of Patent: February 22, 2011
    Assignee: University of South Florida
    Inventors: Shekhar Bhansali, Abdur Rub Abdur Rahman, Sunny Kedia