Patents Examined by Antonio B Crite
  • Patent number: 10854581
    Abstract: A die stack assembly includes first and second power semiconductor device dice. The first die has a P type peripheral edge separation structure that extends from the top planar semiconductor surface of the first die all the way to the bottom planar semiconductor surface of the die, and that is doped at least in part with aluminum. The backside of the first die is mounted to the backside of the second die. A metal feature that is not covered with passivation, and that can serve as a bonding pad, is disposed on part of the peripheral edge separation structure. A metal member (for example, a bond wire or metal clip) contacts the metal feature such that an electrical connection is established from the metal member, through the metal feature, through the peripheral edge separation structure of the first die, and to an electrode of the second die.
    Type: Grant
    Filed: May 8, 2020
    Date of Patent: December 1, 2020
    Assignee: Littelfuse, Inc.
    Inventors: Elmar Wisotzki, Frank Ettingshausen
  • Patent number: 10847747
    Abstract: A display device according to an embodiment of the present invention includes: one or a plurality of display elements provided in a display region; and an organic sealing film provided above the display element in the display region and a picture-frame region outside the display region, the organic sealing film being formed of an organic insulating material, the organic sealing film including, in at least a portion of the picture-frame region, a high surface portion whose surface is higher than a surface of the organic sealing film in the display region.
    Type: Grant
    Filed: March 29, 2018
    Date of Patent: November 24, 2020
    Assignee: Japan Display Inc.
    Inventor: Shinji Nakajima
  • Patent number: 10831174
    Abstract: A method for adaptable machining includes (a) providing one or more images with a digital imaging system of each of a series of work pieces, (b) for each of the work pieces, selectively modifying a preprogrammed cutting tool path with regard to the image of the respective work piece, and (c) for each of the work pieces, performing a machining operation according to the respective selectively modified preprogrammed cutting tool path.
    Type: Grant
    Filed: July 22, 2019
    Date of Patent: November 10, 2020
    Inventor: Michael Scott, Jr.
  • Patent number: 10804117
    Abstract: A method of aligning semiconductor dies having metallic bumps in a mold chase for further processing. A plurality of semiconductor dies are placed in the mold chase at approximately desired locations for further processing. A plurality of magnets in a retainer are associated with the mold chase, the plurality of magnets being associated with respective ones of the plurality of semiconductor dies. The magnetic field of the magnets is applied to align and hold the plurality of dies at the desired location. The plurality of magnets may be adjustably mounted in the retainer so that they can be adjusted to more precisely align the semiconductor dies at the desired locations.
    Type: Grant
    Filed: March 27, 2018
    Date of Patent: October 13, 2020
    Assignee: Intel Corporation
    Inventors: Digvijay Ashokkumar Raorane, Ravindranath V. Mahajan
  • Patent number: 10804154
    Abstract: A wafer processing method includes a grouping step of dividing a wafer along division lines demarcating a plurality of devices as one block on the wafer to form a plurality of group pieces, a reattaching step of attaching one of the group pieces to an expansion tape, a modified layer forming step of emitting a laser beam having a wavelength transmittable through the wafer along the division lines for each group piece to form modified layers, a dividing step of expanding the expansion tape, and dividing each of the group pieces in which the modified layers are formed into individual devices.
    Type: Grant
    Filed: March 1, 2019
    Date of Patent: October 13, 2020
    Assignee: DISCO CORPORATION
    Inventor: Jinyan Zhao
  • Patent number: 10797019
    Abstract: A semiconductor package structure includes at least one semiconductor die, at least one conductive pillar, an encapsulant and a circuit structure. The semiconductor die has an active surface. The conductive pillar is disposed adjacent to the active surface of the semiconductor die. The encapsulant covers the semiconductor die and the conductive pillar. The encapsulant defines at least one groove adjacent to and surrounding the conductive pillar. The circuit structure is electrically connected to the conductive pillar.
    Type: Grant
    Filed: August 22, 2017
    Date of Patent: October 6, 2020
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Hsu-Nan Fang, Chun-Jun Zhuang
  • Patent number: 10770635
    Abstract: This disclosure discloses a light-emitting device. The light-emitting device includes a light-emitting stack with a first (top) surface, a bottom surface and at least one side surface connected to the first surface and the bottom surface, a light-reflective enclosure with a second (top) surface, a contact electrode formed on the bottom surface of the light-emitting layer, and a wavelength converting layer. Moreover, the light-reflective enclosure surrounds the side surface of the light-emitting stack and exposes to the first surface. The wavelength converting layer covers the first surface and the second surface. In addition, the second surface has a plurality of fine concave structures distributed on the second surface.
    Type: Grant
    Filed: May 22, 2019
    Date of Patent: September 8, 2020
    Assignee: Epistar Corporation
    Inventors: Chien-Liang Liu, Ming-Chi Hsu, Jen-Chieh Yu
  • Patent number: 10770630
    Abstract: A light-emitting device includes: a substrate; a light-emitting element above the substrate; a plate-shaped light-transmissive member having a lower surface that faces the upper surface of the light-emitting element; and a covering member. The upper surface of the light-emitting element has a rectangular shape so as to have a first lateral side and a second lateral side opposite to each other. An upper surface of the light-transmissive member has a rectangular shape having a first lateral side and a second lateral side opposite to each other. In a plan view from above the light-emitting device, the first lateral side of the upper surface of the light-transmissive member is outside the first lateral side of the upper surface of the light-emitting element, and the second lateral side of the upper surface of the light-transmissive member is inside the second lateral side of the upper surface of the light-emitting element.
    Type: Grant
    Filed: September 26, 2018
    Date of Patent: September 8, 2020
    Assignee: NICHIA CORPORATION
    Inventor: Tomonori Miyoshi
  • Patent number: 10763171
    Abstract: An embodiment of the present disclosure provides a method of manufacturing a semiconductor apparatus, including the following steps.
    Type: Grant
    Filed: February 6, 2019
    Date of Patent: September 1, 2020
    Assignee: OKAMOTO MACHINE TOOL WORKS, LTD.
    Inventors: Eiichi Yamamoto, Takahiko Mitsui
  • Patent number: 10763415
    Abstract: Disclosed is a method for manufacturing a semiconductor light emitting device, the method including: providing a mask having a plurality of openings on a base; placing semiconductor light emitting chips on exposed portions of the base through the openings, respectively, by a device carrier which recognizes a shape of the mask and calibrates position for a semiconductor light emitting chip to be seated; and supplying an encapsulant to each of the openings, with the mask serving as a dam.
    Type: Grant
    Filed: July 23, 2019
    Date of Patent: September 1, 2020
    Assignee: SEMICON LIGHT CO., LTD.
    Inventors: Soo Kun Jeon, Seung Ho Baek, Da Rae Lee, Bong Hwan Kim, Dong So Jung
  • Patent number: 10753567
    Abstract: A light source unit for a car lamp. The light source unit includes a substrate including wiring electrodes; a plurality of semiconductor light emitting devices electrically connected to the wiring electrodes; a plurality of phosphor portions spaced apart at preset intervals and arranged along rows and columns, and respectively disposed between the semiconductor light emitting devices so as to convert light emitted by surrounding semiconductor light emitting devices into second light having a second wavelength and to emit the second light; a light transmitting material filled between the phosphor portions and emitting first light having a first wavelength; and a color filter covering the phosphor portions and the light transmitting material and emitting the first light with the first wavelength and the second light with the second wavelength.
    Type: Grant
    Filed: October 4, 2018
    Date of Patent: August 25, 2020
    Assignee: LG ELECTRONICS INC.
    Inventors: Sungwhan Lee, Hooyoung Song
  • Patent number: 10755971
    Abstract: A method of manufacturing a semiconductor device by performing a process on a substrate includes: forming a protective layer made of a polymer having a urea bond by supplying a raw material for polymerization to a surface of a substrate on which a protected film to be protected is formed; forming a sealing film at a first temperature lower than a second temperature at which the polymer is depolymerized so cover a portion where the protective layer is exposed; subsequently, subjecting the substrate to a treatment at a third temperature equal to or higher than the second temperature at which the polymer as the protective layer is depolymerized; subsequently, performing a treatment which causes damage to the protected film when the protective layer is not present; and after the performing a treatment which causes damage to the protected film, depolymerizing the polymer by heating the substrate.
    Type: Grant
    Filed: September 6, 2019
    Date of Patent: August 25, 2020
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Tatsuya Yamaguchi, Reiji Niino, Hiroyuki Hashimoto, Syuji Nozawa, Makoto Fujikawa
  • Patent number: 10739879
    Abstract: In various embodiments, bilayers are formed in electronic devices at least in part by anodization of metal-alloy base layers.
    Type: Grant
    Filed: January 18, 2018
    Date of Patent: August 11, 2020
    Assignee: H.C. STARCK INC.
    Inventors: Helia Jalili, Francois Dary, Barbara Cox
  • Patent number: 10734362
    Abstract: A die stack assembly includes first and second power semiconductor device dice. The first die has a P type peripheral edge separation structure that extends from the top planar semiconductor surface of the first die all the way to the bottom planar semiconductor surface of the die, and that is doped at least in part with aluminum. The backside of the first die is mounted to the backside of the second die. A metal feature that is not covered with passivation, and that can serve as a bonding pad, is disposed on part of the peripheral edge separation structure. A metal member (for example, a bond wire or metal clip) contacts the metal feature such that an electrical connection is established from the metal member, through the metal feature, through the peripheral edge separation structure of the first die, and to an electrode of the second die.
    Type: Grant
    Filed: June 11, 2017
    Date of Patent: August 4, 2020
    Assignee: Littelfuse, Inc.
    Inventors: Elmar Wisotzki, Frank Ettingshausen
  • Patent number: 10734367
    Abstract: A semiconductor package includes upper and lower semiconductor chip packages, and a redistribution wiring layer pattern interposed between the packages. The lower package includes a molding layer in which at least one chip is embedded, and has a top surface and an inclined sidewall surface along which the redistribution wiring layer pattern is formed. The upper and lower packages are electrically connected to through the redistribution wiring layer pattern. A first package may be formed by a wafer level packaging technique and may include a redistribution wiring layer as a substrate, a semiconductor chip disposed on the redistribution wiring layer, and a molding layer on which the lower package, redistribution wiring layer pattern and upper package are disposed.
    Type: Grant
    Filed: December 26, 2018
    Date of Patent: August 4, 2020
    Assignee: Sansumg Electronics Co., Ltd.
    Inventors: Seung-Kwan Ryu, Yonghwan Kwon, Yun Seok Choi, Chajea Jo, Taeje Cho
  • Patent number: 10720424
    Abstract: An ESD protection device includes a substrate structure having a substrate, first and second fins, and first and second doped regions having different conductivity types. The first doped region includes a first portion of the substrate and a first region of the first fin, the second doped region includes a second portion of the substrate, a second region of the first fin adjacent to the first region and the second fin. The ESD device also includes a first gate structure on a surface portion of the first region and on an entire surface of the second region of the first fin and including, from bottom to top, an interface layer on the surface portion of the first region and the surface portion of the second region of the first fin, a spacer, a high-k dielectric layer, a first work-function adjusting layer, a second work-function adjusting layer, and a gate.
    Type: Grant
    Filed: November 2, 2018
    Date of Patent: July 21, 2020
    Assignees: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION, SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING) CORPORATION
    Inventor: Yong Li
  • Patent number: 10707132
    Abstract: After forming a material stack including a gate dielectric, a work function metal and a cobalt gate electrode in a gate cavity formed by removing a sacrificial gate structure, the cobalt gate electrode is recessed by oxidizing the cobalt gate electrode to provide a cobalt oxide layer on a surface of the cobalt gate electrodes and removing the cobalt oxide layer from the surface of the cobalt gate electrodes by a chemical wet etch. The oxidation and oxide removal steps can be repeated until the cobalt gate electrode is recessed to any desired thickness. The work function metal can be recessed after the recessing of the cobalt gate electrode is completed or during the recessing of the cobalt gate electrode.
    Type: Grant
    Filed: August 30, 2019
    Date of Patent: July 7, 2020
    Assignees: International Business Machines Corporation, GlobalFoundries Inc., LAM Research Corporation
    Inventors: Georges Jacobi, Vimal K. Kamineni, Randolph F. Knarr, Balasubramanian Pranatharthiharan, Muthumanickam Sankarapandian
  • Patent number: 10692855
    Abstract: An ESD protection device structure compatible with CMOS process is disclosed. In the ESD protection device structure, a power source I/O unit or a signal I/O unit of an I/O circuit is electrically connected to an electrostatic discharge clamp circuit including multiple low-voltage PMOS structure are formed in the P-type substrate and connected in series. Source and gate on low voltage N-type well of first low-voltage PMOS structure are electrically connected to a high-voltage power terminal pad through a first power line, or electrically connected to a signal transmission terminal pad through a signal transmission line, and drain of final low-voltage PMOS structure is electrically connected to a high voltage ground terminal pad through second power line. The ESD protection device structure using the serially-connected low-voltage PMOS structures only, can use the circuit layout area more efficiently and provide high ESD tolerance.
    Type: Grant
    Filed: May 22, 2018
    Date of Patent: June 23, 2020
    Assignee: EGALAX_EMPIA TECHNOLOGY INC.
    Inventors: Po-Chuan Lin, Shr-Hau Shiue
  • Patent number: 10679937
    Abstract: Devices and methods of fabricating integrated circuit devices for forming low resistivity interconnects are provided. One method includes, for instance: obtaining an intermediate semiconductor interconnect device having a substrate, a cap layer, and a dielectric matrix including a set of trenches and a set of vias; depositing a barrier layer along a top surface of the semiconductor interconnect device; depositing and annealing a metal interconnect material over a top surface of the barrier layer, wherein the metal interconnect material fills the set of trenches and the set of vias; planarizing a top surface of the intermediate semiconductor interconnect device; exposing a portion of the barrier layer between the set of trenches and the set of vias; and depositing a dielectric cap. Also disclosed is an intermediate device formed by the method.
    Type: Grant
    Filed: October 17, 2017
    Date of Patent: June 9, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Xunyuan Zhang, Frank W. Mont, Errol Todd Ryan
  • Patent number: 10680101
    Abstract: A semiconductor device includes: a first semiconductor region disposed over a second semiconductor region, wherein the first and second semiconductor regions have a first doping type and a second doping type, respectively; a first source/drain contact region and a second source/drain contact region having the second doping type and laterally spaced; and a gate electrode disposed laterally between the first and second source/drain contact regions, wherein the gate electrode comprises a first sidewall relatively closer to the first source/drain region and a second sidewall relatively closer to the second source/drain region, and wherein respective cross-sectional areas of the first and second sidewalls of the gate electrode are different from each other.
    Type: Grant
    Filed: July 31, 2017
    Date of Patent: June 9, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Wan-Jyun Syue, Chin-Yi Huang, Kuo-Lung Tzeng, Zhuo-Cang Yang