Abstract: A pixel includes a first insulating film disposed on a substrate, a light emitting element disposed on the first insulating film, a second insulating film disposed on the light emitting element to cover at least a portion of the light emitting element, a first contact electrode and a second contact electrode, each of the first and second contact electrodes including at least a portion disposed on the first insulating film and connected to the light emitting element, and an encapsulation layer including a photosensitive material.

Abstract: Various embodiments of the present disclosure are directed towards a method for forming an integrated chip, where the method includes forming an interconnect structure over a first substrate. A dielectric structure is formed over the interconnect structure. The dielectric structure comprises opposing sidewalls defining an opening. A conductive bonding structure is formed on a second substrate. A bonding process is performed to bond the conductive bonding structure to the interconnect structure. The conductive bonding structure is disposed in the opening. The bonding process defines a first cavity between inner opposing sidewalls of the conductive bonding structure and a second cavity between the conducive bonding structure and the opposing sidewalls of the dielectric structure.

Abstract: A LED structure includes a substrate, a bonding layer, a first doping type semiconductor layer, a multiple quantum well (MQW) layer, a second doping type semiconductor layer, a passivation layer and an electrode layer. The bonding layer is formed on the substrate, and the first doping type semiconductor layer is formed on the bonding layer. The MQW layer is formed on the first doping type semiconductor layer, and the second doping type semiconductor layer is formed on the MQW layer. The second doping type semiconductor layer includes an isolation material made through implantation, and the passivation layer is formed on the second doping type semiconductor layer. The electrode layer is formed on the passivation layer in contact with a portion of the second doping type semiconductor layer through a first opening on the passivation layer.

Abstract: A light-emitting device comprises a transparent substrate, a reflection structure and a light-emitting unit. The transparent substrate is defined with a first surface and a second surface opposite to each other. The reflection structure is disposed on and contacts the second surface of the transparent substrate. The reflection structure includes a reflection layer and a circuit layer. The reflection structure is configured to define a light-transmitting window. The light-emitting unit is disposed corresponding to the light-transmitting window. The light-emitting unit is electrically connected to the circuit layer of the reflection structure, and one optical path of the light-emitting unit passes through the light-transmitting window.

Abstract: An integrated optically functional multilayer structure includes a flexible, substrate film arranged with a circuit design including at least a number of electrical conductors preferably additively printed on the substrate film; a light source provided upon a first side of the substrate film to internally illuminate at least portion of the structure for external perception; an optically transmissive plastic layer produced upon the first side of the substrate film, said plastic layer at least laterally surrounding, the light source, the substrate film at least having a similar or lower refractive index therewith; and a reflector design comprising at least one material layer, said reflector design being configured to reflect, the light emitted by the light source and incident upon the reflector design.

Abstract: A display device includes a substrate including pixels, a first electrode and a second electrode disposed on the substrate and spaced apart from each other, an inclined pattern disposed on the first electrode and the second electrode, the inclined pattern forming a space, and a first light emitting element disposed between the first electrode and the second electrode inside of the space formed by the inclined pattern.

Abstract: An integrated LED package structure light source includes: a plurality of LED package structure bodies. The plurality of LED package structure bodies each include a BT plate, a positive-electrode terminal, a negative-electrode terminal, LED light-emitting chips, a control integrated circuit (IC), and a package colloid. The BT plate is made of a light-transmissive BT material. The BT plate and an LED chip packaged on one side of the BT plate allow light of the LED chip to be transmitted through the periphery and top end of the package colloid and the back side of the BT plate, thereby improving the light-emitting dead angle, achieving comprehensive light-emitting, reducing the production cost, improving the device practicability, facilitating port distribution rules, and achieving the structure and connection simplicity. Moreover, LEDs can be directly and quickly connected through connection wires, and the external control IC is not required anymore, reducing the manufacturing cost.

Abstract: A semiconductor device with large memory capacity is provided. A semiconductor device includes first to fourth insulators, a first conductor, a second conductor, and a first semiconductor, and the first semiconductor includes a first surface and a second surface. A first side surface of the first conductor is included on the first surface of the first semiconductor, and a first side surface of the first insulator is included on a second side surface of the first conductor. The second insulator is included in a region including a second side surface and a top surface of the first insulator, a top surface of the first conductor, and the second surface of the first semiconductor. The third insulator is included on a formation surface of the second insulator, and the fourth insulator is included on a formation surface of the third insulator. The second conductor is included in a region overlapping the second surface of the first semiconductor in a region where the fourth insulator is formed.

Abstract: The present application provides a manufacturing method of a semiconductor structure, and relates to the technical field of semiconductors. The manufacturing method includes: providing a substrate; and forming multiple spaced first isolation sidewall structures on the substrate, where first opening regions are formed between adjacent first isolation sidewall structures, and each of the first opening regions is used to expose at least two columns of active regions.

Abstract: Provided are a display substrate and a preparation method thereof, and a display apparatus. The display substrate includes a plurality of sub-pixels, and a pixel drive circuit in the sub-pixel includes a drive transistor and a storage capacitor; the display substrate includes a semiconductor layer, a first conductive layer and a second conductive layer which are sequentially disposed on a substrate; the semiconductor layer at least includes an active layer of a drive transistor; the first conductive layer at least includes a first electrode plate; and the second conductive layer at least includes a second electrode plate and an electrode plate connection line, wherein the electrode plate connection line is connected to a second electrode plate in an adjacent sub-pixel in a first direction.

Abstract: The present disclosure relate to a semiconductor light emitting device and a method for manufacturing the same. The semiconductor light emitting device comprises a semiconductor light emitting chip, and first electrodes electrically connected to the semiconductor light emitting chip, with the first electrodes each having a planar area larger than that of the semiconductor light emitting chip, wherein lower surfaces of the first electrodes are exposed externally, and an insulating material is filled in-between inner lateral surfaces of the first electrodes.

Abstract: A micro-LED chip includes multiple micro-LEDs. At least one micro-LED of the multiple micro-LEDs includes: a first type conductive layer; a second type conductive layer stacked on the first type conductive layer; and a light emitting layer formed between the first type conductive layer and the second type conductive layer. The light emitting layer extends along a horizontal level from a top edge of the first type conductive layer and a bottom edge of the second type conductive layer. The micro-LED chip further includes a metal layer formed on a portion of the light emitting layer that extends from the top edge of the first type conductive layer.

Abstract: Embodiments include semiconductor packages. A semiconductor package includes first and second bottom dies on a package substrate, first top dies on the first bottom die, and second top dies on the second bottom die. The semiconductor package includes thermally conductive slugs on the first bottom die and the second bottom die. The thermally conductive slugs are comprised of a high thermal conductive material. The thermally conductive slugs are positioned directly on outer edges of top surfaces of the first and second bottom dies, inner edges of the top surfaces of the first and second bottom dies, and/or a top surface of the package substrate. The high thermal conductive material of the thermally conductive slugs is comprised of copper, silver, boron nitride, or graphene. The thermally conductive slugs may have two different thicknesses. The semiconductor package may include an active die and/or an integrated heat spreader with the pedestals.

Abstract: The present disclosure relates to a semiconductor device and a manufacturing method thereof, and more particularly to an interlayer dielectric (ILD) layer in a semiconductor device. In one example, the ILD layer is over a substrate and includes a dielectric with a dielectric constant of less than about 3.3 and a hardness of at least about 3 GPa. The semiconductor device also includes an interconnect formed in the ILD layer.

Abstract: Embodiments of 3D memory devices are disclosed. In an example, a 3D memory device includes a memory stack, a structure penetrating the memory stack; a dielectric stack on the memory stack, and a contact structure penetrating the dielectric stack and being in contact with the structure. The dielectric stack comprises a first dielectric layer and a second dielectric layer having a first dielectric material, and an intermedia dielectric layer sandwiched by the first dielectric layer and the second dielectric layer, and having a second dielectric material different from the first dielectric material. The contact structure comprises a lower contact portion penetrating the first dielectric layer and the intermedia dielectric layer, the lower contact portion having a first lateral dimension, and an upper contact portion penetrating the second dielectric layer, the upper contact portion having a second lateral dimension less than the first lateral dimension.

Abstract: A micro multi-color LED device includes two or more LED structures for emitting a range of colors. The two or more LED structures are vertically stacked to combine light from the two more LED structures. Light from the micro multi-color LED device is emitted substantially vertically upward through each of the LED structures. In some embodiments, each LED structure is connected to a pixel driver and/or a common electrode. The LED structures are bonded together through bonding layers. In some embodiments, planarization layers enclose each of the LED structures or the micro multi-color LED device. In some embodiments, one or more of reflective layers, refractive layers, micro-lenses, spacers, and reflective cup structures are implemented in the device to improve the LED emission efficiency. A display panel comprising an array of the micro tri-color LED devices has a high resolution and a high illumination brightness.

Abstract: An electronic device including a substrate and at least one light emitting unit is provided. The at least one light emitting unit is disposed on the substrate. The at least one light emitting unit includes a light emitting diode and a protective layer. The protective layer includes a portion overlapped with the light emitting diode, and the portion has a concave part adjacent to an edge of the light emitting diode in a top view of the electronic device.

Abstract: A display substrate and a display device are provided. The display substrate includes: a base substrate, a pixel driving circuit layer, a first planarization layer, an anode layer, a light emitting functional layer, and a spacer. The first planarization layer includes a first via hole, the anode layer includes a first anode and a second anode, the first anode includes a first main body portion and a first connection portion, the second anode includes a second main body portion and a second connection portion, the spacer is located between the first and second main body portions in adjacent anode group rows. An overlapping area between the spacer and the first via hole is less than 20% of an area of the first via hole.

Abstract: A semiconductor device is provided. The semiconductor device includes a substrate which includes a cell region and a core region, a boundary element separation film which is placed inside the substrate, and separates the cell region and the core region, and a bit line which is placed on the cell region and the boundary element separation film and extends along a first direction, in which the boundary element separation film includes a first region and a second region, a height of an upper side of the first region of the boundary element separation film is different from a height of an upper side of the second region of the boundary element separation film, on a basis of a bottom side of the boundary element separation film, and the bit line is placed over the first region and the second region of the boundary element separation film.

Abstract: The present disclosure relates to a radio frequency device that includes a device region with a back-end-of-line (BEOL) portion and a front-end-of-line (FEOL) portion, first bump structures, a first mold compound, and a second mold compound. The FEOL portion includes an active layer, a contact layer, and isolation sections. Herein, the active layer and the isolation sections reside over the contact layer, and the active layer is surrounded by the isolation sections. The BEOL portion is formed underneath the FEOL portion, and the first bump structures and the first mold compound are formed underneath the BEOL portion. Each first bump structure is partially encapsulated by the first mold compound, and electrically coupled to the FEOL portion via connecting layers within the BEOL portion. The second mold compound resides over the active layer without a silicon material, which has a resistivity between 5 Ohm-cm and 30000 Ohm-cm, in between.