Abstract: A computer system in which only the cache memory is permitted to communicate with main memory and the same address being used in the cache is also sent at the same time to the main memory. Thus, as soon as it is discovered that the desired main memory address is not presently in the cache, the main memory RAMs can be read to the cache without being delayed by the main memory address set up time. In addition, since the main memory is not accessable other than from the cache memory, there is also no main memory access delay caused by requests from other system modules such as the I/O controller. Likewise, since the contents of the cache memory is written into a temporary register before being sent to the main memory, a main memory read can be performed before doing a writeback of the cache to the main memory, so that data can be back to the cache in approximately the same amount of time required for a normal main memory access.

Abstract: The print interrupt control codes are contained in the document. The printing is stopped when the print interrupt control code is detected during printing the document, and a train of characters is newly prepared under this condition. The printing operation is interrupted when the print interrupt control code appears during the printing which is performed in accordance with the document data stored in the temporary storage means, and whereby the input processing means is placed in operation so that the new train of characters can be input and processed. The word processor has function to print the newly prepared train of characters when the printing is resumed, and to easily effect the insert printing.

Abstract: A technique for providing automatic modification of a computer application program adopts the program for compatibility with hardware different from that for which the program was originally written and tested. Upon initial loading of the application program, a search is made to determine the existence of a set of exception tables, external to the application program. If the exception tables are present, all code conversion tables within the application program relating to I/O operations are modified according to the set of exception tables. Plural sets of exception tables may be included with the ability of the operator to choose which set of exception tables will be used to modify the program, thereby allowing the operator to use a single program with a variety of different hardwawre configurations, assuring with each configuration that the intended characters and symbols are displayed and printed.

Abstract: A computer system has a central processing unit and a video display processor both of which must directly access the system memory. The display processor must access the memory once in a given time period which time period is long enough that several accesses by the central processing unit and the display processor would be possible. The system includes a memory controller which allows the central processing unit to have memory access priority over the display processor, as long as sufficient time remains in the period for the display processor to complete its access after the access by the processing unit. If insufficient time remains, the display processor has priority for memory access. To implement this priority scheme, a new system memory organization is employed, dividing the memory into banks or bit planes and providing each bank with a respective temporary storage latch that loads to a respective shift register.

Abstract: An interlock of an instruction processing pipeline in a data processing system responsive to the validity of the pipeline stages within the instruction unit pipeline under microprogram control, is provided. Thus, a microprogram can provide for the release of a particular pipeline stage based on a selected characteristic of the valid signals generated by other stages of the pipeline. An interlock control signal is generated by a decode of a field in a microinstruction stored in a control store RAM or through hardwired decoding.

Abstract: In a multi-tier computer system, a database configuration message is transmitted from a cell controlling computer to a database cache computer to designate certain data items to be monitored at one or more station-level computers. The database cache computer is connected via a local area network to the station-level computers. The station-level computers monitor the data items and generate unsolicited messages containing changed states for data items which have changed over the monitoring period. The database cache computer receives the unsolicited message and interprets the data therein to update the relevant data items. The unsolicited messages are sent back periodically without the need for polling by the database cache computer. If desired, the data in the unsolicited messages can be limited to data which has changed since the last update of the relevant data items.

Abstract: The improved I/O controller includes a data processing element for executing a sequence of stored program instructions to control the transfer of data between respective ones of a plurality of I/O devices and the host computer. The controller further includes a memory element for storing the program instructions and parameter tables associated with the transfer of data. A first sequence of stored program instructions defines a first communications protocol and a second sequence of stored program instructions defines a second communications protocol. A first control table is associated with a first I/O device, for relating the first device to the first program instructions and a second control table is associated with a second I/O device, for relating the second I/O device to the second program instructions.

Abstract: A method of performing an input/output process containing a programmed input/output (PIO) instruction in a multiprocessor system including at least two processors each having an associated I/O bus with I/O devices connected thereto. The method has the steps of storing a unique address and a bus location for each I/O device in a device location table, determining the address of a referenced I/O device prior to performing the PIO instruction, reading the corresponding I/O bus location of the referenced I/O device from the device location table and executing the input/output process on the prescribed processor associated with the I/O bus to which the referenced I/O device is located. The method is used in conjunction with a task scheduler including a process control block for each scheduled process. When the PIO instruction references a device on the local I/O bus, the input/output process is executed normally.

Abstract: A slave processor adapted to execute a read/write operation in response to a read/write request signal from a master processor, comprises a first circuit for performing a write operation during a predetermined period of time from the moment a first write request signal is made inactive from an active condition. An second circuit is provided for generating, when another access request signal such as a second write request signal or a read request signal is made active during the above predetermined period of time, an active wait signal requiring the master processor to maintain the second access request signal in an active condition. The second circuit also operates to delay an operation indicated by the second access request signal.

Abstract: System for analyzing programs by measuring the degree of code coverage of a program being tested during specific test phases. A correlation and comparison of results obtained from both a static and dynamic analysis recording is made. The introduction of a static and dynamic instruction flow indicator permits a determination of the test cover results by correlating the data of the static and dynamic instruction flow indicators. Thus, the number of untested functions can be determined during a test phase of a computer program before sending the data processing system to the field.

Abstract: Control logic for controlling references to a cache (24) including a cache directory (62) which is capable of being configured into a plurality of ways, each way including tag and valid-bit storage for associatively searching the directory (62) for cache data-array addresses. A cache-configuration register and control logic (64) splits the cache directory (62) into two logical directories, one directory for controlling requests from a first processor and the other directory for controlling requests from a second processor. A prefetch buffer (63) is provided along with a prefetch control register for splitting the prefetch buffer into two logical channels, a first channel for handling prefetches associated with requests from the first processor, and a second channel for handling prefetches associated with requests from the second processor.

Abstract: A system for controlling the transfer of commands between processors of a multiprocessor system, including a single control unit connected to all the processors by separate information transfer lines. The control unit selects the processor generating a command transfer request signal in a predetermined priority order and receives the processor address from the selected processor. The receiving processor and predetermined transfer information are determined in accordance with the selected processor, the processor address, and the processor status information determined by the processor address. The predetermined transfer information is transferred to the receiving processor via an information transfer path established between the selected processor and the receiving processor.

Abstract: A plurality of data transmitting and receiving devices (1) are inter-connected by an interface bus system configured as two or more sub-bus systems (2,3,4) connected into a chain by a corresponding number of communication links (5). Each sub-bus system (2,3,4) includes a communications arrangement (7) interfacing the sub-bus system with the associated link or links (5). The overall interface bus system operates in accordance with a data transfer protocol that involves a handshake procedure requiring the participation of all active devices (1) connected to the bus system. In order to avoid the whole installation locking up upon one sub-system (3,4) becoming non-responsive, each communication arrangement (7), other than the one associated with the last sub-bus system (4) in the chain, is arranged to check the responsiveness of its down-chain neighbour when requested to do so by a control input from the installation controller (1A).

Abstract: Arbitration circuit operates for common bus access granting where the asynchronous access requests are latched in a register by the rising edge of a periodical square wave timing signal, and from there transferred to a logical priority network, implemented with a programmable logic array.

Abstract: Using a variable-duration clock circuit, together with programmable duration control to alter the clock waveform within strict rules, permits the programmer to arrange appropriately short durations for short data transfers, and to arrange appropriately longer durations for longer data transfers in an array processor of myriad processing elements. There is no need to allow sufficient time in every clock cycle for worst case data transfer between remote processing elements.The clock waveform has three recognizable edges (A,B,C) regardless of loss of sharpness during its travel to the various processing elements. The convention that three skew-sensitive activities, READ, WRITE and OPERAND SUPPLY conform to respectively assigned edges as follows:A=READ;B=OPERAND SUPPLY;C=WRITE (Read next)The processing elements synchronize with the clock waveform, which is optimized for the instructions of the program being executed.

Abstract: An apparatus and method are provided for disabling the clocking of a processor in a battery operated computer during non-processing times. The clocking is disabled at the conclusion of a processing operation. The clocking can then be re-enabled using interrupts from any one of a plurality of sources, such as an I/O device or a direct memory access. Application programs and operating system programs running on the system can specify the stopping of the system clock and the central processor until a specified event which had been requested occurs, or until an optional time-out period has expired. In this situation, the event is defined as one that results in either a system interrupt from an I/O device or from a direct memory access operation. The stopping of the system clock is a two part operation wherein in the first part the stopping mechanism is first armed. If an interrupt is received subsequent to arming, then it will be processed and the arming mechanism will be reset.

Abstract: In the present invention, data input/output equipment is connected in communication with a host machine which provides a plurality of service application programs by designating system parameters of one or more common programs. A mode setting feature designates at least a program setting mode and an execution mode. A program RAM stores at least one common program being loaded from the host machine. A parameter setting feature designates parameters included in the common program loaded in the program setting mode to define a plurality of application programs, each of which is available for a specified service. A parameter RAM memorizes the designated parameters. An entry data RAM memorizes entry data, and a service selecting feature designates one of the application programs in the execution mode.

Abstract: A computer system includes a computer address modification system that is advantageously coupled in a bus network to selectively translate memory address data in 16K blocks and provide DMA page addresses in 16K blocks which may match the 16K memory address blocks. The modification system includes a mapping RAM selectively providing translated addresses to enable addresses in a 16 megabyte extended address space. The modification system also includes a page register storing for each addressable 16K block of data for each DMA channel a page address within the extended address space.

Abstract: An interface circuit can assign a common input/output port address to a plurality of I/O circuits. Each common I/O port is defined in terms of pages. In an actual data input/output, a specific port address is used for port control so as to select one common page. The interface circuit has a first decoder for decoding a specific port address signal. The interface circuit also had a data setter for setting data supplied from a specific bit line of the data bus. The data is set in the data setter in accordance with the decoded signal from the first decoder. Each of the plurality of I/O circuits has a second decoder for decoding the common I/O port address signal. An output from the setter enables a corresponding one of second decoders. As a result, a specific page is selected.

Abstract: A data processing system comprises: an instruction queue memory; an instruction decode unit; an address computation unit; an address translation unit; and an instruction execution unit. Further comprised is a decoded instruction queue memory having a queue structure composed of a plurality of entries for latching an entry information. The decoded instruction queue memory includes: a first counter adapted to be counted up in response to the effective address computation requiring signal of the instruction decode unit and down in response to the translation completion signal of the address translation unit; and a second counter having a counting-down function. When the first and second counters are to be counted down, one closer to the instruction execution unit and having a counted value other than zero is counted down. When the queue is the decoded instruction queue memory advances, the first counter has its counted value copied to that of the second counter and then set at the value of zero.