Patents Examined by Arpan P Savla
  • Patent number: 10013361
    Abstract: A method of managing data in a cache upon a cache write operation includes determining a number of non-contiguously written sectors on a track in the cache and comparing the number with a threshold number. If the number exceeds the threshold number, a full background stage operation is issued to fill the non-contiguously written sectors with unmodified data from a storage medium and the full track is then destaged. A corresponding system includes a cache manager module operating on the storage subsystem. Upon a determination that a cache write operation on a track has taken place, the cache manager module determines a number of non-contiguously written sectors on the track, compares the number with a predetermined threshold number, issues a background stage operation to fill the non-contiguously written sectors with unmodified data from a storage medium if the number exceeds the threshold number, and then destages the full track.
    Type: Grant
    Filed: November 13, 2013
    Date of Patent: July 3, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: David F. Mannenbach, Karl A. Nielsen
  • Patent number: 10013181
    Abstract: Provided are a method, a system, and a computer program product in which a storage controller determines a plurality of parts of a dataset. At least one part of the dataset is stored in a local storage coupled to the storage controller. At least one other part of the dataset in one or more cloud storages coupled to the storage controller.
    Type: Grant
    Filed: December 7, 2015
    Date of Patent: July 3, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Matthew G. Borlick, Lokesh M. Gupta, Roger G. Hathorn, Karl A. Nielsen
  • Patent number: 10007608
    Abstract: A method to store objects in a memory cache is disclosed. A request is received from an application to store an object in a memory cache associated with the application. The object is stored in a cache region of the memory cache based on an identification that the object has no potential for storage in a shared memory cache and a determination that the cache region is associated with a storage policy that specifies that objects to be stored in the cache region are to be stored in a local memory cache and that a garbage collector is not to remove objects stored in the cache region from the local memory cache.
    Type: Grant
    Filed: March 27, 2015
    Date of Patent: June 26, 2018
    Assignee: SAP SE
    Inventors: Galin Galchev, Frank Kilian, Oliver Luik, Dirk Marwinski, Petio Petev
  • Patent number: 10007431
    Abstract: Storage devices including a controller, a first memory coupled to the controller, and a second memory coupled to the controller, wherein the controller is configured to generate a linked list in response to a received access command, the linked list comprising one or more first entries corresponding to user data to be received from or outputted to an external device and one or more second entries for metadata to be generated by the storage device, and having a defined order of the first entries and the second entries corresponding to a defined data structure of a page of data of the first memory.
    Type: Grant
    Filed: February 14, 2017
    Date of Patent: June 26, 2018
    Assignee: Micron Technology, Inc.
    Inventors: Frank Chen, Yuan Rong
  • Patent number: 10001932
    Abstract: A data storage array is presented that includes a plurality of storage drives each comprising storage media with a first storage region and a shingled magnetic recording (SMR) storage region. The data storage array includes a control system communicatively coupled to the storage drives and configured to receive a write operation over a host interface for storage of write data by the data storage array. Responsive to the write operation, the control system is configured to cache the write data in first storage regions of two or more of the storage drives prior to transfer of the write data into at least an SMR storage region of a storage drive associated with the write operation.
    Type: Grant
    Filed: June 9, 2015
    Date of Patent: June 19, 2018
    Assignee: Western Digital Technologies, Inc.
    Inventors: Randall L. Hess, Berck E. Nash, James M. Reiser, Randy L. Roberson, Kris B. Stokes, Jesse L. Yandell
  • Patent number: 10002264
    Abstract: A storage device includes a memory including a first storage area configured to store area information that indicates a geographical area, and a second storage area configured to store data, and a processor coupled to the memory and configured to append data storage information, which indicates a location of the storage device, to the data to be stored in the second storage area, and allow a piece of the data stored in the second storage area to become available, the piece having the data storage information indicating that the location of the storage device falls within an area indicated by the area information, while the storage device is located within the area indicated by the area information.
    Type: Grant
    Filed: December 2, 2013
    Date of Patent: June 19, 2018
    Assignee: FUJITSU LIMITED
    Inventors: Ayumi Takano, Toru Irisawa, Shigeru Ikushima, Takuma Yamada
  • Patent number: 9977732
    Abstract: The disclosure is related to systems and methods of nonvolatile data caching. In some embodiments, circuits or methods may be configured to store selected data to a nonvolatile data cache based on selection criteria. The selection criteria may be based on previous data access commands. The selection criteria may relate an amount of resources, such as time or power, needed to retrieve the selected data from a data storage medium. The selected data may be retrieved from the data storage medium and stored at the nonvolatile data cache during an idle state.
    Type: Grant
    Filed: March 31, 2011
    Date of Patent: May 22, 2018
    Assignee: Seagate Technology LLC
    Inventors: Stanton MacDonough Keeler, Steven Scott Williams, Robert William Dixon
  • Patent number: 9965397
    Abstract: An apparatus having a cache and a circuit is disclosed. The cache includes a plurality of cache lines. The cache is configured to (i) store a plurality of data items in the cache lines and (ii) generate a map that indicates a dirty state or a clean state of each of the cache lines. The cache also has a write-back policy to a memory. The circuit is configured to (i) check a location in the map corresponding to a read address of a read request and (ii) obtain read data directly from the memory by bypassing the cache in response to the location having the clean state.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: May 8, 2018
    Assignee: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
    Inventors: Horia Simionescu, Siddartha Kumar Panda, Kunal Sablok, Veera Kumar Reddy Oleti
  • Patent number: 9959930
    Abstract: A method for writing data into a reprogrammable non-volatile memory, wherein a marking pattern including several bits is added at the beginning of the data and the set formed of the marking pattern and of the data is written from an address in the memory varying from one write operation to another, the marking pattern being identical for each write operation.
    Type: Grant
    Filed: March 30, 2011
    Date of Patent: May 1, 2018
    Assignee: PROTON WORLD INTERNATIONAL N.V.
    Inventors: Gilles Van Assche, Ronny Van Keer
  • Patent number: 9952798
    Abstract: Methods, systems, and apparatus for allocating, by a source of one or more sources, a segment of a data file of a transient memory for exclusive access by the source, the transient memory being a distributed in-memory file system that supports remote direct memory access; writing, by the source, data from an initial partition to one or more blocks within the allocated segment of the data file, wherein a portion of the initial partition is written to a first block of the one or more blocks; publishing, by the source, the segment of the data file of the transient memory to be accessible for reading by one or more sinks; and reading by a particular sink of the one or more sinks, a particular block of the published segment of the data file of the transient memory, wherein the particular block is associated with the particular sink.
    Type: Grant
    Filed: August 12, 2016
    Date of Patent: April 24, 2018
    Assignee: Google Inc.
    Inventors: Hossein Ahmadi, Matthew B. Tolton, Michael Entin
  • Patent number: 9952968
    Abstract: Techniques for distributed cache management are provided. A server having backend resource includes a global cache and a global cache agent. Individual clients each have client cache agents and client caches. When data items associated with the backend resources are added, modified, or deleted in the client caches, the client cache agents report the changes to the global cache agent. The global cache agent records the changes and notifies the other client cache agents to update a status of the changes within their client caches. When the changes are committed to the backend resource each of the statuses in each of the caches are updated accordingly.
    Type: Grant
    Filed: January 29, 2010
    Date of Patent: April 24, 2018
    Assignee: Micro Focus Software, Inc.
    Inventors: Lee Edward Lowry, Brent Thurgood, Stephen R Carter
  • Patent number: 9928057
    Abstract: In one or more embodiments, a method of generating a code by a compiler includes: analyzing a program executed by a processor; analyzing data necessary to execute respective tasks included in the program; determining whether a boundary of the data used by divided tasks is consistent with a management unit of a cache memory based on results of the analyzing; and generating the code for providing a non-cacheable area from which the data to be stored in the management unit including the boundary is not temporarily stored into the cache memory and the code for storing an arithmetic processing result stored in the management unit including the boundary into a non-cacheable area in a case where it is determined that the boundary of the data used by the divided tasks is not consistent with the management unit of the cache memory.
    Type: Grant
    Filed: December 14, 2010
    Date of Patent: March 27, 2018
    Assignee: WASEDA UNIVERSITY
    Inventors: Hironori Kasahara, Keiji Kimura, Masayoshi Mase
  • Patent number: 9898421
    Abstract: A memory access processing method is based on memory chip interconnection, a memory chip, and a system, which relate to the field of electronic devices, and can shorten a time delay in processing a memory access request and improve a utilization rate of system bandwidth. The method of the present disclosure includes receiving, by a first memory chip, a memory access request; and if the first memory chip is not a target memory chip corresponding to the memory access request, sending, according to a preconfigured routing rule, the memory access request to a next memory chip connected with the first memory chip, until the target memory chip corresponding to the memory access request is determined. Embodiments of the present disclosure are mainly used in a process of processing a memory access request.
    Type: Grant
    Filed: June 26, 2015
    Date of Patent: February 20, 2018
    Assignee: HUAWEI TECHNOLOGIES CO., LTD.
    Inventors: Yongbing Huang, Mingyu Chen, Yuan Ruan, Licheng Chen
  • Patent number: 9886386
    Abstract: An apparatus having a cache and a controller is disclosed. The controller is configured to (i) gather a plurality of statistics corresponding to a plurality of requests made from one or more hosts to access a memory during an interval, (ii) store data of the requests selectively in the cache in response to a plurality of headers and (iii) adjust one or more parameters in the headers in response to the statistics. The requests and the parameters are recorded in the headers.
    Type: Grant
    Filed: July 23, 2013
    Date of Patent: February 6, 2018
    Assignee: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
    Inventors: Mark Ish, Sumanesh Samanta
  • Patent number: 9880748
    Abstract: Bifurcated memory management for memory elements techniques are disclosed. In one aspect, a memory element includes a self-managed portion and a portion that is managed by a remote host. Software that needs low latency access may be stored in the portion of the memory element that is managed by the remote host and other software may be stored in the portion of the memory element that is managed by the memory element. By providing such bifurcated memory management of the memory element, a relatively inexpensive memory element may be used to store software while at the same time allowing low latency (albeit at low throughputs) access to sensitive software elements with minimal bus logic.
    Type: Grant
    Filed: February 13, 2015
    Date of Patent: January 30, 2018
    Assignee: QUALCOMM Incorporated
    Inventors: Amit Gil, Assaf Shacham
  • Patent number: 9811421
    Abstract: A method is used in managing multi-step storage management operations. A policy is defined for a task of a multi-step storage management operation. The multi-step storage management operation includes multiple tasks. The policy for the task indicates directions for reacting to results of the task of the multi-step storage management operation. The task is invoked. The policy for the task is invoked based on results of the task.
    Type: Grant
    Filed: March 31, 2011
    Date of Patent: November 7, 2017
    Assignee: EMC IP Holding Company LLC
    Inventors: RongZhang Wu, Xuan Tang, Yifan Wang, Yiyang Zhang
  • Patent number: 9785354
    Abstract: Provided are a computer program product, system, and method for selective write control in accordance with the present description. In one aspect, a write operation which is associated with a read operation, may be selectively discarded if write operations have been disabled and if the write operation is directed to update a designated write operation acceptance area such as metadata associated with the target data set, for example. As a result, the read operation may be permitted to proceed and will not fail because the associated write operation was discarded rather than attempting to commit the write operation to the designated write operation acceptance area, thereby avoiding an error condition for a storage unit such as a volume, in which write operations have been disabled. Accordingly, applications which seek to perform read operations may be permitted to access data stored on such a volume. Other aspects are described.
    Type: Grant
    Filed: June 29, 2015
    Date of Patent: October 10, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Nikhil Khandelwal, Gregory E. McBride, David C. Reed, Richard A. Welp
  • Patent number: 9772781
    Abstract: A method of maintaining and updating a logical-to-physical (LtoP) table in a storage device including a processor, a volatile memory, and a non-volatile memory, the storage device being in communication with a host utilizing atomic writes, the method including receiving, by the processor, data for storing at a plurality of physical addresses in the non-volatile memory, the data being associated with a plurality of logical addresses of the host, storing, by the processor, the plurality of physical addresses in an atomic segment in the volatile memory, storing, by the processor, one or more of zones of the LtoP table in the non-volatile memory, the one or more zones of the LtoP table corresponding in size to the atomic segment, and updating the one or more zones of the LtoP table with the plurality of physical addresses in the atomic segment.
    Type: Grant
    Filed: November 27, 2013
    Date of Patent: September 26, 2017
    Assignee: NGD Systems, Inc.
    Inventors: Nader Salessi, Joao Alcantara
  • Patent number: 9740432
    Abstract: Systems and method relating generally to solid state memory, and more particularly to systems and methods for recycling data in a solid state memory. The systems and methods include receiving a data set maintained in a memory device, applying at least one iteration of a data decoding algorithm to the data set by a data decoder circuit to yield a decoded output, counting the number of iterations of the data decoding algorithm applied to the data set to yield an iteration count, and recycling the data set to the memory device. The recycling is triggered based at least in part on the iteration count.
    Type: Grant
    Filed: August 23, 2016
    Date of Patent: August 22, 2017
    Assignee: SEAGATE TECHNOLOGY LLC
    Inventors: Yu Cai, Yunxiang Wu, Ning Chen, Erich F. Haratsch, Zhengang Chen
  • Patent number: 9715353
    Abstract: Provided are a computer program product, system, and method for an application to provide for, in one embodiment, using hierarchical storage management to respond to a request to delete a data set by migrating the data set to another storage tier in a storage system before deleting the data set from its current location. As a result, the data set is stored on another tier to provide an opportunity to reverse the decision to delete the data set. In one embodiment, a temporary interval of time is provided to reverse the deletion decision and restore the data set from the migrated data set, before the data set is permanently deleted.
    Type: Grant
    Filed: September 16, 2014
    Date of Patent: July 25, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Derek L. Erdmann, Franklin E. McCune, Miguel A. Perez