Patents Examined by Arpan P Savla
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Patent number: 9015400Abstract: A computer system and a method are provided that reduce the amount of time and computing resources that are required to perform a hardware table walk (HWTW) in the event that a translation lookaside buffer (TLB) miss occurs. If a TLB miss occurs when performing a stage 2 (S2) HWTW to find the PA at which a stage 1 (S1) page table is stored, the MMU uses the IPA to predict the corresponding PA, thereby avoiding the need to perform any of the S2 table lookups. This greatly reduces the number of lookups that need to be performed when performing these types of HWTW read transactions, which greatly reduces processing overhead and performance penalties associated with performing these types of transactions.Type: GrantFiled: March 5, 2013Date of Patent: April 21, 2015Assignee: QUALCOMM IncorporatedInventors: Thomas Zeng, Azzedine Touzni, Tzung Ren Tzeng, Phil J. Bostley
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Patent number: 9009409Abstract: A method to store objects in a memory cache is disclosed. A request is received from an application to store an object in a memory cache associated with the application. The object is stored in a cache region of the memory cache based on an identification that the object has no potential for storage in a shared memory cache and a determination that the cache region is associated with a storage policy that specifies that objects to be stored in the cache region are to be stored in a local memory cache and that a garbage collector is not to remove objects stored in the cache region from the local memory cache.Type: GrantFiled: July 12, 2011Date of Patent: April 14, 2015Assignee: SAP SEInventors: Galin Galchev, Frank Kilian, Oliver Luik, Dirk Marwinski, Petio G. Petev
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Patent number: 9003119Abstract: In a storage apparatus, in the case where a data block to be written to a storage medium is a zero data block containing only zero data, a zero data information memory stores zero data identification information indicating that the data block is a zero data block. A control apparatus receives a data block from an access requesting apparatus in association with a write request issued by the access requesting apparatus for writing the data block a specified number of times to a predetermined storage area of the storage medium, and when determining that the data block is a zero data block containing only zero data, sets zero data identification information in the zero data information memory, and when completing the setting of the zero data identification information, sends the access requesting apparatus a completion notice of the writing to the storage medium.Type: GrantFiled: January 9, 2012Date of Patent: April 7, 2015Assignee: Fujitsu LimitedInventors: Motohiro Sakai, Akihito Kobayashi
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Patent number: 8984240Abstract: Page faults during partition migration from a source computing system to a destination computing system are reduced by assigning each page used by a process as being hot or cold according to their frequency of use by the process. During a live partition migration, the cold or coldest (least frequently used) pages are copied to the destination server first, followed copying the warmer (less frequently used) and concluded by copying the hottest (most frequently used) pages. After all dirtied pages have been refreshed, cutover from the instance on the source server to the destination server is made. By transferring the warm and hot pages last (or later) in the migration process, the number of dirtied pages is reduced, thereby reducing page faults subsequent to the cutover.Type: GrantFiled: August 30, 2012Date of Patent: March 17, 2015Assignee: International Business Machines CorporationInventors: Vishal C. Aslot, Adekunle Bello, Brian W. Hart
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Patent number: 8954697Abstract: A system configures page tables to cause an operating system to copy original page data in a data store when any one of the application processes makes a first write request for the original page data. The system detects a page fault from a memory management unit receiving a first write request from one of the application processes and creates the copy in physical memory to allow the application process to modify the page data copy. The other application processes have read access to the original page data. The system replaces the original page data in the data store with the page data copy in response to receiving a first synchronization request from the application process and updates a page table for one of the other application processes to configure access to the replaced page data in response to receiving a second synchronization request from the one other application process.Type: GrantFiled: August 5, 2010Date of Patent: February 10, 2015Assignee: Red Hat, Inc.Inventors: Neil R. T. Horman, Eric L. Paris, Jeffrey T. Layton
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Patent number: 8949566Abstract: Methods, apparatuses, and computer program products are provided for locking access to data storage shared by a plurality of compute nodes. Embodiments include maintaining, by a compute node, a queue of requests from requesting compute nodes of the plurality of compute nodes for access to the data storage, wherein possession of the queue represents possession of a mutual-exclusion lock on the data storage, the mutual-exclusion lock indicating exclusive permission for access to the data storage; and conveying, based on the order of requests in the queue, possession of the queue from the compute node to a next requesting compute node when the compute node no longer requires exclusive access to the data storage.Type: GrantFiled: December 2, 2010Date of Patent: February 3, 2015Assignee: International Business Machines CorporationInventors: Madhusudanan Kandasamy, Vidya Ranganathan, Murali Vaddagiri
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Patent number: 8949510Abstract: By assigning a slave unit and at least one master unit in a buffer controller, clocks of the at least one master unit can be unified with a clock of the slave unit. A buffer status array is assigned for the slave unit in a buffer, and either a range status array or a queue status array is assigned for the master unit in the buffer for performing operations of the buffer controller in an accessing-by-block manner or in an accessing-by-spaced-interval manner. The master unit cooperated with the slave unit is determined from the at least one master unit by using a starvation-preventing algorithm.Type: GrantFiled: January 9, 2012Date of Patent: February 3, 2015Assignee: Skymedi CorporationInventors: Li-Hsiang Chan, Po-Yen Liu
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Patent number: 8949545Abstract: A data processing device includes a load/store module to provide an interface between a processor device and a bus. In response to receiving a load or store instruction from the processor device, the load/store module determines a predicted coherency state of a cache line associated with the load or store instruction. Based on the predicted coherency state, the load/store module selects a bus transaction and communicates it to the bus. By selecting the bus transaction based on the predicted cache state, the load/store module does not have to wait for all pending bus transactions to be serviced, providing for greater predictability as to when bus transactions will be communicated to the bus, and allowing the bus behavior to be more easily simulated.Type: GrantFiled: December 4, 2008Date of Patent: February 3, 2015Assignee: Freescale Semiconductor, Inc.Inventor: John D. Pape
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Patent number: 8949540Abstract: A victim cache line having a data-invalid coherence state is selected for castout from a first lower level cache of a first processing unit. The first processing unit issues on an interconnect fabric a lateral castout (LCO) command identifying the victim cache line to be castout from the first lower level cache, indicating the data-invalid coherence state, and indicating that a lower level cache is an intended destination of the victim cache line. In response to a coherence response to the LCO command indicating success of the LCO command, the victim cache line is removed from the first lower level cache and held in a second lower level cache of a second processing unit in the data-invalid coherence state.Type: GrantFiled: March 11, 2009Date of Patent: February 3, 2015Assignee: International Business Machines CorporationInventors: Guy L. Guthrie, Hien M. Le, Alvan W. Ng, Michael S. Siegel, Derek E. Williams, Phillip G. Williams
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Patent number: 8930616Abstract: System refresh in a cache memory that includes generating a refresh time period (RTIM) pulse at a centralized refresh controller of the cache memory and activating a refresh request at the centralized refresh controller based on generating the RTIM pulse. The refresh request is associated with a single cache memory bank of the cache memory. A refresh grant is received and transmitted to a bank controller. The bank controller is associated with and localized at the single cache memory bank of the cache memory.Type: GrantFiled: October 18, 2012Date of Patent: January 6, 2015Assignee: International Business Machines CorporationInventors: Michael A. Blake, Timothy C. Bronson, Hieu T. Huynh, Kenneth D. Klapproth
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Patent number: 8930645Abstract: Methods and apparatus facilitate data streaming in bulk storage devices by generating linked lists containing entries for both user data and metadata. These linked lists containing mixed data types facilitate receiving and outputting user data, and to insert or ignore, respectively, metadata corresponding to that user data without interrupting flow of the user data.Type: GrantFiled: December 4, 2008Date of Patent: January 6, 2015Assignee: Micron Technology, Inc.Inventors: Frank Chen, Yuan Rong
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Patent number: 8918588Abstract: Techniques for replacing one or more blocks in a cache, the one or more blocks being associated with a plurality of data streams, are provided. The one or more blocks in the cache are grouped into one or more groups, each corresponding to one of the plurality of data streams. One or more incoming blocks are received. To free space, the one or more blocks of the one or more groups in the cache are invalidated in accordance with at least one of an inactivity of a given data stream corresponding to the one or more groups and a length of the one or more groups. The one or more incoming blocks are stored in the cache. A number of data streams maintained within the cache is maximized.Type: GrantFiled: April 7, 2009Date of Patent: December 23, 2014Assignee: International Business Machines CorporationInventors: Brian Bass, Giora Biran, Hubertus Franke, Amit Golander, Hao Yu
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Patent number: 8886895Abstract: A method for fetching information in response to hazard indication information, the method includes: (i) associating hazard indication information to at least one information unit that is being fetched to the cache module; (ii) receiving a request to perform a fetch operation; and (iii) determining whether to fetch at least one information unit to the cache module in response to the hazard indication information and in response to dirty information associated with the at least one information unit.Type: GrantFiled: September 14, 2004Date of Patent: November 11, 2014Assignee: Freescale Semiconductor, Inc.Inventors: Itay Peled, Moshe Anschel, Jacob Efrat, Alon Eldar, Ziv Zamsky
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Patent number: 8886891Abstract: Accessing a shared buffer can include receiving an identifier associated with a buffer from a sending process, requesting one or more attributes corresponding to the buffer based on the received identifier, mapping at least a first page of the buffer in accordance with the one or more requested attributes, and accessing an item of data stored in the buffer by the sending process. The identifier also can comprise a unique identifier. Further, the identifier can be passed to one or more other processes. Additionally, the one or more requested attributes can include at least one of a pointer to a memory location and a property describing the buffer.Type: GrantFiled: March 26, 2008Date of Patent: November 11, 2014Assignee: Apple Inc.Inventors: Kenneth Christian Dyke, Jeremy Todd Sandmel, Geoff Stahl, John Kenneth Stauffer
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Patent number: 8868848Abstract: A computer system may comprise a computer platform and input-output devices. The computer platform may include a plurality of heterogeneous processors comprising a central processing unit (CPU) and a graphics processing unit (GPU) and a shared virtual memory supported by a physical private memory space of at least one heterogeneous processor or a physical shared memory shared by the heterogeneous processor. The CPU (producer) may create shared multi-version data and store such shared multi-version data in the physical private memory space or the physical shared memory. The GPU (consumer) may acquire or access the shared multi-version data.Type: GrantFiled: December 21, 2009Date of Patent: October 21, 2014Assignee: Intel CorporationInventors: Ying Gao, Hu Chen, Shoumeng Yan, Xiaocheng Zhou, Sai Luo, Bratin Saha
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Patent number: 8850129Abstract: A system and computer implemented method for storing of data in the memory of a computer system in order at a fast rate is provided. The method includes launching a first store to memory. A wait counter is initiated. A second store to memory is speculatively launched when the wait counter expires. The second store to memory is cancelled when the second store achieves coherency prior to the first store to memory.Type: GrantFiled: June 24, 2010Date of Patent: September 30, 2014Assignee: International Business Machines CorporationInventors: Norbert Hagspiel, Matthias Klein, Ulrich Mayer, Robert J. Sonnelitter, III, Gary E. Strait, Hanno Ulrich
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Patent number: 8812805Abstract: A mixed storage device includes a set of storage units, each potentially based on a different storage technology, such as NAND flash drive, NOR flash drive, magnetic hard drive, magneto-optical drives, optical drives, etc. The mixed storage device comprises a host bus connector that is used to connect to a peripheral bus that facilitates communication to a processor of a device (such as a PC) and a controller. The controller manages a NAND flash storage device, a NOR flash storage device, an optical storage device, a hard drive and other storage components plugged into or integrated with the mixed storage device.Type: GrantFiled: December 3, 2008Date of Patent: August 19, 2014Assignee: Broadcom CorporationInventor: James D. Bennett
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Patent number: 8799599Abstract: Described is a method and system for transparently migrating data between storage systems of a computing environment without disrupting realtime access to the stored data of the storage systems. Specifically, when adding a new storage system to the computing environment, realtime data write operations can be redirected to the new storage system instead of an existing storage system. During the redirection, the data stored on the existing storage system can be accessed for data operations. Concurrently, during the redirection, data stored on the existing storage system can be migrated to the new storage system. When the data migration completes and all the data, stored on the existing storage system prior to the redirection, resides on the new storage system, the new storage system can function as the primary storage system. Thus, storage capacity can increase or be replaced without disrupting data operations.Type: GrantFiled: May 9, 2012Date of Patent: August 5, 2014Assignee: International Business Machines CorporationInventors: Catherine Moriarty Nunez, Martine Bruce Wedlake
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Patent number: 8793448Abstract: Described is a method and system for transparently migrating data between storage systems of a computing environment without disrupting realtime access to the stored data of the storage systems. Specifically, when adding a new storage system to the computing environment, realtime data write operations can be redirected to the new storage system instead of an existing storage system. During the redirection, the data stored on the existing storage system can be accessed for data operations. Concurrently, during the redirection, data stored on the existing storage system can be migrated to the new storage system. When the data migration completes and all the data, stored on the existing storage system prior to the redirection, resides on the new storage system, the new storage system can function as the primary storage system. Thus, storage capacity can increase or be replaced without disrupting data operations.Type: GrantFiled: July 29, 2010Date of Patent: July 29, 2014Assignee: International Business Machines CorporationInventors: Martine Bruce Wedlake, Catherine Moriarty Nunez
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Patent number: 8793465Abstract: Method and system for correcting misalignment between a virtual storage device block and a storage device block is provided. To align the blocks, an alignment module adjusts a logical block address and updates virtual storage device information such that a virtual machine can use a virtual storage device with the aligned blocks.Type: GrantFiled: March 9, 2010Date of Patent: July 29, 2014Assignee: Netapp, Inc.Inventors: Eric P. Forgette, Jonathan H. Dascenzo