Abstract: Profile properties in a partition profile are user-configurable through a management entity such as a management console. A partition manager calculates a secondary processing unit entitlement for a logical partition based in part on a secondary processing unit mode property in the partition profile. The secondary processing unit entitlement may be smaller than a primary processing unit entitlement for the logical partition. The partition manager reserves processing units from a secondary shared processor pool equal to the logical partition's secondary entitlement for the logical partition. The primary and secondary processing unit entitlements may be stored in primary and secondary configuration data structures associated with the logical partition. The partition manager may relocate the logical partition to the secondary shared processor pool in response to a predetermined condition.

Abstract: The present invention discloses a data accessing method and an apparatus for performing the method. Through a newly-defined host logical unit (HLUN), a unique HLUN number is given to each LUN-to-LD/Partition mapping relationship, and the HLUN is present to external hosts. Therefore, all of the hosts in the same storage system may recognize different logical units (i.e., HLUN). Hence, when processing an Input/Output (IO) request issued from any one host, a storage virtualization controller (SVC) can correctly find the corresponding LD/Partition for accessing data without identifying the identity of the host.

Abstract: Embodiments relate to determining the logical address of a transaction abort. In an embodiment, one or more instructions are received are received from an application. The one or more instructions are executed within a first transaction. The first transaction delays committing stores to memory until it has completed. At least one of the one or more instructions includes a first logical memory address. The first logical memory address corresponds to a first memory address in a memory system. It is determined if the first memory address is equal to a second memory address that is stored in a conflict register. Based on determining that they are equal the first logical memory address is saved as a logical address associated with a cross invalidate (XI) signal at a location available to the application.

Abstract: A technique is provided for monitoring a value without repeated storage access. A processing circuit processes an instruction of a program that specifies a memory address of a memory location to be monitored. The processing circuit configures a monitor station for monitoring the memory location. The memory location includes a state descriptor for the program. The processing circuit receives a cross-invalidate request from a memory controller. The cross-invalidate request indicates to the monitor station that content of the memory location has been changed by another processing circuit.

Abstract: A technique that supports improved debugging of kernel loadable modules (KLMs) that involves allocating a first portion of a memory and detecting a first kernel loadable module (KLM) requesting an allocation of at least a portion of the memory. The first KLM is then loaded into the first portion of the memory and a first identifier is associated with the first KLM and the first portion. The access of a second portion of the memory by the first KLM, the second portion being distinct from the first portion is detected and an indication that the first KLM has accessed the second portion is generated.

Abstract: A storage management solution according to certain embodiments is provided which decouples certain aspects of the storage manager from the data storage cell. The data storage system according to certain aspects can provide one or more external storage managers that manage data protection and administer the operation of data storage cells. According to certain aspects, usage of the decoupled storage manager can be allocated amongst multiple data storage cells, such as by data storage cells of multiple companies, sub-units of a company, or both.

Abstract: A method for implementing embedded dynamic random access memory (eDRAM) refreshing in a high performance cache architecture. The method includes receiving a memory access request, via a cache controller, from a memory refresh requestor, the memory access request for a memory address range in a cache memory. The method also includes detecting that the cache memory located at the memory address range is available to receive the memory access request and sending the memory access request to a memory request interpreter. The method further includes receiving the memory access request from the cache controller, determining that the memory access request is a request to refresh contents of the memory address range in the cache memory, and refreshing data in the memory address range.

Abstract: A data storage device and a Flash memory control method. A data storage device comprises a Flash memory and a controller. The controller controls the Flash memory in accordance with firmware. When the firmware is available for at least a predetermined time period without being requested by a host, the controller, driven according to the firmware, performs a garbage-collection operation on the Flash memory without a request from the host.

Abstract: Digital objects are stored and accessed within a fixed content storage cluster by using a page mapping table and a pages index. A stream is read from the cluster by using a portion of its unique identifier as a key into the page mapping table. The page mapping table indicates a node holding a pages index indicating where the stream is stored. A stream is written by storing the stream on any suitable node and then updating a pages index stored within the cluster responsible for knowing the location of digital objects having unique identifiers that fall within a particular address range. The cluster recovers from a node failure by first replicating streams from the failed node and reallocating a page mapping table to create a new pages index. The remaining nodes send records of the unique identifiers corresponding to objects they hold to the new pages index.

Abstract: The invention concerns a solid state memory, comprising multiple logical units. The solid state memory contains an internal buffer for temporarily storing the incoming data steam before the incoming data are programmed to at least one page. The internal buffer keeps data that are not yet programmed in case a switch from one logical unit to another is performed. A method for operating such a device is presented.

Abstract: A memory management and protection system that manages memory access requests from a number of requestors. Memory accesses are allowed or disallowed based on the privilege level of the master, usually a CPU originating the request based on a Privilege Identifier that accompanies each memory access request. Deputy masters such as DMA controllers inherit the Privilege Identifier of the originating master. An extended memory controller selects the appropriate set of segment registers based on the Privilege Identifier to insure that the request is compared to and translated by the segment register associated with the master originating the request.

Abstract: In response to a request received from a guest alignment module, host alignment module determines a target starting location in a virtual hard disk to which the beginning of a guest partition of a virtual machine is written. Host alignment module translates a guest partition's virtual hard disk address into a physical hard disk address and determines whether the physical hard disk address is track aligned with disk tracks of the physical hard disk. If the physical hard disk address is not track aligned, host alignment module determines a new track aligned physical hard disk address as the target starting location. If the physical hard disk address is track aligned, the same physical hard disk address is used as the target starting location. The target starting location is returned to the guest alignment module as a new virtual hard disk address.

Abstract: A memory refresh requestor, a memory request interpreter, a cache memory, and a cache controller on a single chip. The cache controller configured to receive a memory access request, the memory access request for a memory address range in the cache memory, detect that the cache memory located at the memory address range is available, and send the memory access request to the memory request interpreter when the memory address range is available. The memory request interpreter configured to receive the memory access request from the cache controller, determine if the memory access request is a request to refresh a contents of the memory address range, and refresh data in the memory address range when the memory access request is a request to refresh memory.

Abstract: Digital objects are stored and accessed within a fixed content storage cluster by using a page mapping table and a pages index. A stream is read from the cluster by using a portion of its unique identifier as a key into the page mapping table. The page mapping table indicates a node holding a pages index indicating where the stream is stored. A stream is written to the cluster by storing the stream on any suitable node and then updating a pages index stored within the cluster. The cluster recovers from a node failure by first replicating streams from the failed node and reallocating a page mapping table to create a new pages index. The remaining nodes send records of the unique identifiers corresponding to objects they hold to the new pages index. A node is added to the cluster by reallocating a page mapping table.

Abstract: A data processing apparatus includes: an instruction execution section; an instruction protection information storage section that stores instruction protection information for specifying at least one partial address space in an instruction address space for storing instructions executed by the instruction execution section; a data protection information storage section that stores data protection information for specifying multiple partial address spaces in a data address space for storing operands for use in an operation of the instruction execution section; and a protection violation determination section that determines whether to permit access from the instruction execution section based on setting of the instruction and data protection information storage sections.

Abstract: A method of operation of a non-volatile memory management system includes: selecting a specific time period by a unit controller; establishing a first time pool having super blocks written during the specific time period; and promoting to a second time pool, the super blocks from the first time pool, at the lapse of the specific time period.

Abstract: In one embodiment, a method includes receiving metadata corresponding to data on a removable storage device/medium, storing the metadata to a metadata repository that is not on the removable storage device/medium, associating an identifier with the stored metadata (the identifier corresponding to the removable storage medium/device), and storing the identifier to the metadata repository. According to another embodiment, a computer program product includes a computer readable storage medium having computer readable program code embodied therewith. The computer readable program code comprises computer readable program code configured to: receive metadata corresponding to data on a removable storage device/medium, store the metadata to a metadata repository, associate an identifier corresponding to the removable storage device/medium with the stored metadata, and store the identifier to the metadata repository. Other methods, systems, and devices are presented as well.

Abstract: A hardware data prefetcher includes a queue of indexed storage elements into which are queued strides associated with a stream of temporally adjacent load requests. Each stride is a difference between cache line offsets of memory addresses of respective adjacent load requests. Hardware logic calculates a current stride between a current load request and a newest previous load request. The hardware logic compares the current stride and a stride M in the queue and compares the newest of the queued strides with a queued stride M+1, which is older than and adjacent to stride M. When the comparisons match, the hardware logic prefetches a cache line whose offset is the sum of the offset of the current load request and a stride M?1. Stride M?1 is newer than and adjacent to stride M in the queue.

Abstract: A method of identifying a cache line of a cache memory (180) for replacement, is disclosed. Each cache line in the cache memory has a stored sequence number and a stored transaction data stream identifying label. A request (e.g., 400) associated with a label identifying a transaction data stream is received. The label corresponds to the stored transaction data stream identifying label of the cache line. The stored sequence number of the cache line is compared with a response sequence number. The response sequence number is associated with the stored transaction data stream identifying label of the cache line. The cache line is identified for replacement based on the comparison.

Abstract: A method of controlling a storage device, the method including calculating, in a controller of the storage device, data throughput of the storage device in a current period, comparing, in the controller, the data throughput to a reference value and adjusting, with the controller, an operation performance of the storage device in a next period based on the comparison and a delay factor of a period prior the current period.