Abstract: A read request, a write request, and copy descriptor are constructed and sent to logical volumes of a device stack to complete a copy-offload operation between a source logical volume and a destination logical volume. The read request is forwarded to a source physical volume of a device stack and a write request is forwarded to a destination physical volume of the device stack. Responsive to detecting that the read request has been received by the source physical volume of the device stack and the write request has been received by a destination physical volume of the device stack, the driver of the source physical volume or the driver of the destination physical volume construct a copy-offload request to be sent to a storage device, the copy-offload request comprising the read request, the write request, and the copy descriptor. The copy-offload request is subsequently sent to the storage device.

Abstract: A computer system may comprise a computer platform and input-output devices. The computer platform may include a plurality of heterogeneous processors comprising a central processing unit (CPU) and a graphics processing unit (GPU) and a shared virtual memory supported by a physical private memory space of at least one heterogeneous processor or a physical shared memory shared by the heterogeneous processor. The CPU (producer) may create shared multi-version data and store such shared multi-version data in the physical private memory space or the physical shared memory. The GPU (consumer) may acquire or access the shared multi-version data.

Abstract: Apparatuses and methods for providing data from a buffer are disclosed herein. An example apparatus may include an array, a buffer, and a memory control unit. The buffer may be coupled to the array and configured to store data. The memory control unit may be coupled to the array and the buffer. The memory control unit may be configured to cause the buffer to store the data responsive, at least in part, to a first write command and may further be configured to cause the buffer to store the data in the array responsive, at least in part, to a flush command. The memory control unit may further be configured to interrupt the flush command to prepare for a read command or a second write command and resume the flush command once the read command or the second write command is performed.

Abstract: A latch signal is received from a non-volatile memory device that is indicative of a current access time for the non-volatile memory device. The access time represents an amount of time required for the non-volatile memory device to make data available responsive to a request for data. A bus system clock signal is received. The latch signal is evaluated and a wait state for the non-volatile memory device is adjusted based on the evaluation. The wait state represents a number of cycles of the bus system clock used by a central processing unit for an access of the non-volatile memory device. A bus system data ready signal that is triggered based on the adjusted wait state is produced. The bus system data ready signal, when triggered, indicates that data is available responsive to the request.

Abstract: Embodiments relate to a prefetch threshold for cache restoration. An aspect includes determining, based on a task switch from an outgoing task to a current task in a processor, a prefetch threshold for a next task, the prefetch threshold corresponding to an expected runtime of the current task and an amount of time required to prefetch data for the next task. Another aspect includes starting prefetching for the next task while the current task is executing based on the prefetch threshold.

Abstract: Various systems and methods for performing incremental backups in transactional file systems. For example, one method involves performing the first stage of a multi-stage write operation, where the write operation writes a data block. The method then involves performing a backup operation. However, the backup operation does not backup the modified block, since not all stages of the multi-stage write operation have been performed. The method involves updating metadata to indicate that though the data block was modified and a backup operation was performed, the data block was not included in the backup operation. After all stages of the multi-stage write operation have completed, e.g., a transaction is committed, a subsequent backup operation is performed. The data block is backed up during the subsequent backup operation.

Abstract: An example method includes receiving a request to change a page size managed by a translation lookaside buffer (TLB), wherein the TLB is currently managing a first page size, and the request specifies a second page size different than the first page size; in response to the request: determining a number of lower-order bits for addressing memory location within pages of the second page size; and configuring the TLB to perform lookups within the memory subsystem using a number of higher-order bits for addressing pages of the second page size, wherein the number of higher-order bits is dependent on the number of lower-order bits.

Abstract: A method and circuit arrangement selectively perform regular expression matching in connection with accessing data with a processing unit based upon one or more regular expression matching-related attributes stored in a memory address translation data structure such as an Effective To Real Translation (ERAT) or Translation Lookaside Buffer (TLB). A regular expression matching-related attribute in such a data structure may be used to control whether data being communicated between the processing unit and a communications bus is routed through an expression engine integrated with the processing unit such that regular expression matching may be performed in association with the data communication.

Abstract: The method of the present invention includes the steps of: receiving a command for creating a snapshot of the logical volume; preparing a management table for managing the snapshot; detecting the storage status of the logical volume; and updating the management table without recalling the logical volume from the second level storage to the first level storage when the logical volume has migrated from the first level storage to the second level storage. After the update, the storage table indicates whether creation of a snapshot is required, whether a logical volume has migrated, and whether the second level storage is the storage location of the logical volume.

Abstract: Various embodiments for data management in a storage grid, by a processor device, are provided. In one embodiment, a method comprises directing data Input/Output (I/O) operations from a host to an owning node according to a Logical Block Address (LBA) without a static assignment of ownership, notwithstanding any relationship between the host and the storage grid.

Abstract: Techniques are disclosed for processing a self-steering storage command via a point-to-point communication protocol. A network adapter in a storage node receives an instance of a current command frame directed to a group of storage nodes and performs a storage operation in response to a storage command associated with the current command frame. The network adapter determines whether all storage nodes have received an instance of the current command frame. If all storage nodes have received an instance of the current command frame, then the network adapter transmits a final completion status frame to a computation node that originated the current command frame. Otherwise, the network adapter generates a next instance of the command frame, and transmits the next instance of the current command frame to an additional storage node in the group of storage nodes.

Abstract: A system, method, and computer program product are provided for receiving an incoming data stream. The system comprises a multi-core processor with a memory unit that is configured to include a circular queue that receives a data stream. The circular queue is divided into a plurality of sub-queues determined as a multiple of the number of processing cores, and each sub-queue is assigned to one processing core such that as data is received into a region covered by a particular sub-queue, the processing core assigned to the particular sub-queue processes the data. The system is also configured to update a head pointer and a tail pointer of the circular queue. The head pointer is updated as data is received into the circular queue and the tail pointer is updated by a particular processing core as it processes data in its assigned sub-queue.

Abstract: An apparatus includes a first cache memory, a second cache memory, and a processor coupled to the first cache memory and the second cache memory, and configured to store data in the second cache memory, the data being deleted from the first cache memory, store first data stored in a first address of the storage device, in the second cache memory, in case where the first address is included in first management information and is not included in second management information, according to a request for access to the first address of the storage device, the first management information including an address in the storage device of specific data stored in the storage device, and the second management information including an address in the storage device of data stored in both of the second cache memory and the storage device, and register the first address in the second management information.

Abstract: Cache miss rates for threads operating in a simultaneous multi-threading computer processing environment can be estimated. The single thread rates can be estimated by monitoring a shared directory for cache misses for a first thread. Memory access requests can be routed to metering cache directories associated with the particular thread. Single thread misses to the shared directory and single thread misses to the associated metering cache directory are monitored and a performance indication is determined by comparing the cache misses with the thread misses. The directory in the associated metering cache is rotated, and a second sharing performance indication is determined.

Abstract: A data processing apparatus includes an instruction execution section, a protection control information storage section that stores protection control information that includes first protection information, and second protection information that is independent of the first protection information, an instruction protection information storage section that stores instruction protection information for specifying a partial address space of an instruction address space in which to store instructions that are executable by the instruction execution section, a data protection information storage section that stores data protection information for specifying partial address spaces of a data address space in which to store operands to be usable by the instruction execution section, and a protection violation determination section which, when the first protection information includes a first value, makes a determination as to whether to permit the instruction execution section to access the instruction address space a

Abstract: Cache miss rates for threads operating in a simultaneous multi-threading computer processing environment can be estimated. The single thread rates can be estimated by monitoring a shared directory for cache misses for a first thread. Memory access requests can be routed to metering cache directories associated with the particular thread. Single thread misses to the shared directory and single thread misses to the associated metering cache directory are monitored and a performance indication is determined by comparing the cache misses with the thread misses. The directory in the associated metering cache is rotated, and a second sharing performance indication is determined.

Abstract: Some embodiments of the invention relate to selecting a data protection scheme, such as, for example, mirroring or RAID, for a content unit based on power-related metadata associated with the content unit. The data protection strategy selected for a content unit may impact the amount of power that a storage system consumes.

Abstract: A data storage device is disclosed comprising a non-volatile memory (NVM). During a read operation, a sequence of signal samples is generated representing codewords stored in the NVM. The signal samples are buffered to generate buffered signal samples. The buffered signal samples are processed at a first frequency to detect a data sequence, and a bottleneck condition is detected associated with processing the buffered signal samples at the first frequency. When the bottleneck condition is detected, the buffered signal samples are processed at a second frequency higher than the first frequency to detect the data sequence.

Abstract: A data storage apparatus has a transmission interface, a nonvolatile memory and a controller. The controller records a non-completed flag. When the controller starts a card opening process, the nonvolatile memory is configured under card opening, and the non-completed flag is set non-completed status. When the controller receives a format command form the transmission interface, the nonvolatile memory is formatted and the non-completed flag is set as completed status. When the controller receives a write command, the write data are scrambled before being written to the nonvolatile memory. When in non-completed status, when the controller receives a read command from the transmission interface, no matter whether the data corresponding to the requested address are scrambled, the data are descrambled and descrambled are provided via the transmission interface.

Abstract: Methods facilitate data streaming in bulk storage devices by generating linked lists containing entries for both user data and metadata. These linked lists containing mixed data types facilitate receiving and outputting user data, and to insert or ignore, respectively, metadata corresponding to that user data without interrupting flow of the user data.