Abstract: A method for managing data, the method includes: providing a write-back cache unit coupled to at least one storage unit; receiving a request to write a new data version to a certain cache data allocation unit; determining, in response to a data storage policy, whether to overwrite a cached data version being cached in the certain cache data allocation unit or to perform a destage of the cached data version to a first storage unit before writing the new data version to the certain cache allocation unit; receiving a request to read a data version that corresponds to a certain point in time and scanning a first data structure representative of write operations and a second data structure representative of revert operations to determine a location of the requested data version.

Abstract: A system and methodology that can prevent errors during data commit on multicycle pass complete associated with a memory is provided. The system employs a transaction buffer component in the memory that receives and temporarily stores information associated with a transaction. A controller component programs subsets of data to respective memory locations once the entire transaction is completed based on the information stored in the transaction buffer component. Thus, if the transaction is interrupted during the transfer of the user data into the buffer, the data stored in the memory is not affected and can still contain the original data when power is regained. If the data transfer between the transaction buffer component and memory array is interrupted, the controller component can complete the transfer from the point of interruption on regaining power and can avoid partial storage of data.

Abstract: Flash memory drives and related methods are disclosed that operate to keep frequently written data, which results in frequently erased blocks, in SLC-mimicking MLC flash, and relatively static data in normal MLC flash. A flash drive according to the present disclosure keeps track of the number of times that data for each logical block address (LBA) has been written to the flash memory, and determines whether to store newly received data associated with a particular LBA in SLC-mimicking MLC flash or in normal MLC flash depending on the number of writes that have occurred for that particular LBA. Dynamic allocation can occur between the two types of MLC. Related methods and software are also described.

Abstract: A primary storage controller is configured to communicate with a secondary storage controller via a system data mover. In response to receiving a command to perform a point in time copy of a source volume of the primary storage controller to a target volume of the primary storage controller, a determination is made as to whether the target volume of the primary storage controller is a source for an asynchronous data replication operation, initiated by the system data mover, between the primary storage controller and the secondary storage controller. In response to determining that the target volume of the primary storage controller is the source for the asynchronous data replication operation, initiated by the system data mover, the point in time copy of the source volume of the primary storage controller to the target volume of the primary storage controller is performed.

Abstract: A storage subsystem coupled to a host computer is described. The storage subsystem includes storage devices and first and second storage apparatuses that control data transfer between the host computer and the storage devices. The first storage apparatus includes a first controller coupled to the host computer via a first host communication control unit and to the storage devices via a first storage device communication control unit. The second storage apparatus includes a second controller coupled to the host computer via a second host communication control unit and to the storage devices via a second storage device communication control unit. At least one of the controllers monitors a status of the first host communication control unit and the storage device communication control units, and, if the status of the first storage device communication unit indicates failure, switch communication paths for transferring data from the host computer to the storage devices.

Abstract: An access control device, which increases memory access efficiency to data stored in a memory, includes a plurality of groups of the memory, and divides and stores the data in different memory areas of the plurality of groups of the memory, distinguished based on predetermined bits of an access address. The access control device accesses the data stored in the different memory areas simultaneously in the same clock cycle of access to the memory. The predetermined bits of the access address are controlled independently for each of the groups of the memory. The part of the access address other than the predetermined bits controlled independently for each of the groups is common for the plurality of groups. Modes can be selected to access two horizontally or vertically consecutive unit data or data on vertically alternate lines at a time. The data may be image data or pixel data.

Abstract: An apparatus and method for improving synchronization between threads in a multi-core processor system are provided. An apparatus includes a memory, a first processor core, and a second processor core. The memory includes a shared ring buffer for storing data units, and stores a plurality of shared variables associated with accessing the shared ring buffer. The first processor core runs a first thread and has a first cache associated therewith. The first cache stores a first set of local variables associated with the first processor core. The first thread controls insertion of data items into the shared ring buffer using at least one of the shared variables and the first set of local variables. The second processor core runs a second thread and has a second cache associated therewith. The second cache stores a second set of local variables associated with the second processor core.

Abstract: A primary storage controller is configured to communicate with a secondary storage controller via a system data mover. In response to receiving a command to perform a point in time copy of a source volume of the primary storage controller to a target volume of the primary storage controller, a determination is made as to whether the target volume of the primary storage controller is a source for an asynchronous data replication operation, initiated by the system data mover, between the primary storage controller and the secondary storage controller. In response to determining that the target volume of the primary storage controller is the source for the asynchronous data replication operation, initiated by the system data mover, the point in time copy of the source volume of the primary storage controller to the target volume of the primary storage controller is performed.

Abstract: Method, system, and computer program product embodiments for throttling storage initialization for data destage in a computing storage environment are provided. An implicit throttling operation is performed by limiting a finite resource of a plurality of finite resources available to a background initialization process, the background initialization process adapted for performing the storage initialization ahead of a data destage request. If a predefined percentage of the plurality of finite resources is utilized, at least one of the plurality of finite resources is deferred to a foreground process that is triggered by the data destage request, the foreground process adapted to perform the storage initialization ahead of a data destage performed pursuant to the data destage request. An explicit throttling operation is performed by examining a snapshot of storage activity occurring outside the background initialization process.

Abstract: Embodiments of an invention for generating multiple address space identifiers per virtual machine to switch between protected micro-contexts are disclosed. In one embodiment, a method includes receiving an instruction requiring an address translation; initiating, in response to receiving the instruction, a page walk from a page table pointed to by the contents of a page table pointer storage location; finding, during the page walk, a transition entry; storing the address translation and one of a plurality of address source identifiers in a translation lookaside buffer, the one of the plurality of address source identifiers based on one of a plurality of a virtual partition identifiers, at least two of the plurality of virtual partition identifiers associated with one of a plurality of virtual machines; and re-initiating the page walk.

Abstract: A method is described for preserving the flexibility associated with relative memory addressing in programs designed to be stored in read-only memory.

Abstract: A device and methods are provided for accessing memory. In one embodiment, a method includes receiving a request for data stored in a device, checking a local memory for data based on the request to determine if one or more blocks of data associated with the request are stored in the local memory, and generating a memory access request for one or more blocks of data stored in a memory of the device based when one or more blocks of data are not stored in the local memory. In one embodiment, data stored in memory of the device may be arranged in a configuration to include a plurality of memory access units each having adjacent lines of pixel data to define a single line of memory within the memory access units. Memory access units may be configured based on memory type and may reduce the number of undesired pixels read.

Abstract: A device for storing data includes a sequence generator configured to generate a first number sequence that is a pseudorandom number sequence, a cross-correlation unit configured to produce a second number sequence that is a cross-correlation between the first number sequence and a third number sequence, and a write and read unit configured to write the second number sequence in memory and read the second number sequence from the memory, wherein the cross-correlation unit is further configured to reconstruct the third number sequence by obtaining a cross-correlation between the first number sequence and the second number sequence read from the memory.

Abstract: A network memory system is disclosed. The network memory system comprises a first appliance configured to encrypt first data, store the encrypted first data in a first memory device. The first appliance also determines whether the encrypted first data exists in a second appliance and transmits a store instruction comprising the encrypted first data based on the determination that the encrypted first data does not exist in the second appliance. The second appliance is configured to receive the store instruction from the first appliance and store the encrypted first data in a second memory device. The second appliance is further configured to receive a retrieve instruction comprising a location indicator indicating where the encrypted first data is stored, process the retrieve instruction to obtain encrypted response data, and decrypt the encrypted response data.

Abstract: The disclosure is related to systems and methods of controlling wear of a memory. In a particular embodiment, a system is disclosed that comprises a memory and a performance governor circuit coupled to the memory. The performance governor circuit is adapted to control a wear of the memory as a function of time.

Abstract: Methods and systems are provided that may include a memory device having a physical nonvolatile memory, a memory space, and a controller. At least a portion of a physical nonvolatile memory may permit a direct read operation of the physical nonvolatile memory and prohibit a direct write operation of the physical nonvolatile memory. A memory space may comprise at least open one write overlay window available after a reset operation. Such a memory space may be adapted to permit at least one read overlay window to be opened that is logically separate from at least one open write overlay window. A controller may be included to open at least one read overlay window.

Abstract: A first log indicating that a system is running is recorded in a second storage unit before a first difference log is recorded in the second storage unit after system startup, and a second log indicating that the system halts is recorded in the second storage unit following the difference log, at the time of normal system halt, and it is judged whether normal system halt has been performed or an incorrect power-off sequence has been performed last time, based on a recorded state of the first and second logs in the second storage unit, at the time of system startup, thereby detecting an incorrect power-off easily and reliably.

Abstract: A data storage device, the data storage device may include: a data storage unit; a system data storage unit that stores an application program, an operating system (OS), and management information related to a processing of the stored data; a system control unit that performs an initialization, a control, and a system setting of the device; a central processing unit (CPU) that performs data processing including data read and data write and processes an instruction word; a random access memory (RAM) that loads the data from the data storage unit and the system data storage unit, loads the instruction word of the CPU, and temporarily stores a data processing result of the processed instruction word; and an output determination unit that determines to output at least one of the data stored in the data storage unit, the application program, and the data processing result.

Abstract: Methods and systems for determining a memory access time are provided. A first phase skew is measured between a first clock signal used by a memory and a second clock signal used as a reference clock signal. Then, a second phase skew is measured between a delayed version of the first clock signal output by the memory when the memory completes a given read operation and the second clock signal. The memory access time is determined based on the first and second phase skews.

Abstract: A compression status bit cache provides on-chip availability of compression status bits used to determine how many bits are needed to access a potentially compressed block of memory. A backing store residing in a reserved region of attached memory provides storage for a complete set of compression status bits used to represent compression status of an arbitrarily large number of blocks residing in attached memory. Physical address remapping (“swizzling”) used to distribute memory access patterns over a plurality of physical memory devices is partially replicated by the compression status bit cache to efficiently integrate allocation and access of the backing store data with other user data.