Abstract: A method for manufacturing a semiconductor device includes bonding a supporting substrate and a first surface of a semiconductor substrate via a bonding layer, processing a second surface of the supporting substrate, opposite to the first surface, to shape the semiconductor substrate into a thin film. After shaping the semiconductor substrate into a thin film, polishing a part of the bonding layer formed at a beveled portion of the supporting substrate or the semiconductor substrate with a first polishing plane to remove the part of the bonding layera A33fter polishing the part of the bonding layer, polishing a remaining part of the bonding layer formed at the beveled portion of the supporting substrate or the semiconductor substrate with a second polishing plane different from the first polishing plane to remove the remaining part of the bonding layer.

Abstract: A bottom protection film for an OLED panel is provided. More particularly, a bottom protection film for an OLED panel, which has excellent alignment process workability and excellent adhesion to an OLED panel, and is capable of preventing static electricity through an antistatic treatment and preventing an electrical short circuit at the same time, and an organic light-emitting display device including the bottom protection film are provided.

Abstract: A flowable chemical vapor deposition method including depositing a dielectric film precursor on a substrate in a flowable form; depositing an oligomerization agent on the substrate; forming a dielectric film from the dielectric film precursor; and curing the dielectric film under a pressure greater than atmospheric pressure. A method including depositing a dielectric film precursor as a liquid on a substrate in the presence of an oligomerization agent; treating the deposited dielectric film precursor to inhibit outgassing; and curing the dielectric film precursor to form a dielectric film. A method including delivering a dielectric film precursor as a vapor to a substrate including gap structures between device features; condensing the dielectric film precursor on the substrate to a liquid; flowing the liquid into the gap structures; and curing the dielectric film precursor under a pressure of 15 pounds per square inch gauge or greater.

Abstract: The present disclosure describes a method and apparatus to adjust a wafer's polishing rate based on the temperature of the air received by the air chambers of a polishing head. The method includes supplying pressurized air to a temperature module coupled to a polishing head. The temperature module adjusts a temperature of the pressurized air that is supplied to the polishing head. The method further includes supplying the one or more air chambers of the polishing head with the temperature controlled pressurized air from the temperature module and polishing the wafer by rotating the wafer against a polishing pad.

Abstract: A method for manufacturing a semiconductor device is provided. A first vertical structure and a second vertical structure are formed on a substrate. The second vertical structure is positioned right next to the first vertical structure. The second vertical structure is positioned right next to the first vertical structure. An insulating layer is formed on the substrate between the first and second vertical structures. A gate metal and a gate dielectric layer, are formed on the first and second vertical structures. A portion of the gate metal, gate dielectric layer, and insulating layer is removed. A portion of the substrate is removed. The portion of the substrate is removed after the gate metal is formed on the first and second vertical structure.

Abstract: According to one embodiment, a method of manufacturing a semiconductor device includes: bonding a first surface of a device substrate on which a device is formed on a first surface to a support substrate via an adhesive; after bonding the device substrate to the support substrate, grinding and thinning a second surface side opposite to the first surface of the device substrate based on an in-plane processing rate at the time of forming a semiconductor substrate by RIE; after thinning the device substrate, forming a hole penetrating the device substrate by RIE; and burying metal in the hole to forma through electrode.

Abstract: Methods and systems for forming complex oxide films are provided. Also provided are complex oxide films and heterostructures made using the methods and electronic devices incorporating the complex oxide films and heterostructures. In the methods pulsed laser deposition is conducted in an atmosphere containing a metal-organic precursor to form highly stoichiometric complex oxides.

Abstract: Metasurface elements, integrated systems incorporating such metasurface elements with light sources and/or detectors, and methods of the manufacture and operation of such optical arrangements and integrated systems are provided. Systems and methods for integrating transmissive metasurfaces with other semiconductor devices or additional metasurface elements, and more particularly to the integration of such metasurfaces with substrates, illumination sources and sensors are also provided. The metasurface elements provided may be used to shape output light from an illumination source or collect light reflected from a scene to form two unique patterns using the polarization of light. In such embodiments, shaped-emission and collection may be combined into a single co-designed probing and sensing optical system.

Abstract: Methods of depositing boron and carbon containing films are provided. In some embodiments, methods of depositing B,C films with desirable properties, such as conformality and etch rate, are provided. One or more boron and/or carbon containing precursors can be decomposed on a substrate at a temperature of less than about 400° C. In some embodiments methods of depositing silicon nitride films comprising B and C are provided. A silicon nitride film can be deposited by a deposition process including an ALD cycle that forms SiN and a CVD cycle that contributes B and C to the growing film.

Abstract: A wafer measurement system for measuring a measurable characteristic of a first measurement target formed on a wafer includes: a memory and a processor. The memory is configured to store an image of the wafer, multiple templates each including at least one line, and a measurement program. The processor is accessible to the memory and is configured to execute multiple modules included in the measurement program. The modules include: a template selection module configured to receive the templates and select a measurement template corresponding to a shape of the first measurement target; a template matching module configured to match the measurement template to the first measurement target; and a measurement module configured to measure the measurable characteristic of the first measurement target based on position information of the measurement template.

Abstract: A wafer composite is provided which includes an auxiliary substrate, a donor substrate and a sacrificial layer formed between the auxiliary substrate and the donor substrate. Functional elements of the semiconductor component are formed in a component layer, including at least one partial layer of the donor substrate. The auxiliary substrate is then separated from the component layer by heat input into the sacrificial layer.

Abstract: The present invention provides a semiconductor device including a semiconductor substrate with a memory cell region and a peripheral region, a gate line in the peripheral region, an etch-stop layer covering the gate line and the semiconductor substrate, a first insulating layer covering the etch-stop layer, two contact plugs disposed on the semiconductor substrate in the peripheral region, two pads disposed on the contact plugs respectively, and a second insulating layer disposed between the pads. The contact plugs are located at two sides of the gate line respectively, and the contact plugs penetrate through the etch-stop layer and the first insulating layer to contact the semiconductor substrate. The second insulating layer is not in contact with the etch-stop layer.

Abstract: Exposure of a gate conductive film covered by an interlayer insulation film in a unit cell portion is reduced when a gate contact region is formed. A method of manufacturing a semiconductor device includes forming a gate conductive film to come in contact with a gate oxide film in a unit cell portion, forming a gate wire to come in contact with the gate oxide film in a termination region, forming a first insulation film on an upper surface of the gate wire in the termination region, subjecting an upper surface of the gate conductive film in the unit cell portion to thermal oxidation with use of the first insulation film as a mask to form a thermal oxide film on the upper surface of the gate conductive film, and forming a second insulation film covering the first insulation film and the thermal oxide film.

Abstract: A cluster tool assembly includes a vacuum transfer module, a process module having a first side connected to the vacuum transfer module. An isolation valve having a first side and a second side, the first side of the isolation valve coupled to a second side of the process module. A replacement station is coupled to the second side of the isolation valve. The replacement station includes an exchange handler and a part buffer. The part buffer includes a plurality of compartments to hold new or used consumable parts. The process module includes a lift mechanism to enable placement of a consumable part installed in the process module to a raised position. The raised position provides access to the exchange handler to enable removal of the consumable part from the process module and store in a compartment of the part buffer. The exchange handler of the replacement station is configured to provide a replacement for the consumable part from the part buffer back to the process module.

Abstract: Methods for forming semiconductor devices, such as FinFETs, are provided. In an embodiment, a fin structure processing method includes removing a portion of a first fin of a plurality of fins formed on a substrate to expose a surface of a remaining portion of the first fin, wherein the fins are adjacent to dielectric material structures formed on the substrate; performing a deposition operation to form features on the surface of the remaining portion of the first fin by depositing a Group III-V semiconductor material in a substrate processing environment; and performing an etching operation to etch the features with an etching gas to form a plurality of openings between adjacent dielectric material structures, wherein the etching operation is performed in the same chamber as the deposition operation.

Abstract: A bond chuck having individually-controllable regions, and associated systems and methods are disclosed herein. The bond chuck comprises a plurality of individual regions that are movable relative to one another in a longitudinal direction. In some embodiments, the individual regions include a first region having a first outer surface, and a second region peripheral to the first region and including a second outer surface. The first region is movable in a longitudinal direction to a first position, and the second region is movable in the longitudinal direction to a second position, such that in the second position, the second outer surface of the second region extends longitudinally beyond the first outer surface of the first region. The bond chuck can be positioned proximate a substrate of a semiconductor device such that movement of the first region and/or second region affect a shape of the substrate, which thereby causes an adhesive on the substrate to flow in a lateral, predetermined direction.

Abstract: A bond chuck having individually-controllable regions, and associated systems and methods are disclosed herein. The bond chuck comprises a plurality of individual regions configured to be individually heated independent of one another. In some embodiments, the individual regions include a first region configured to be heated to a first temperature, and a second region peripheral to the first region and configured to be heated to a second temperature different than the first temperature. In some embodiments, the bond chuck further comprises (a) a first coil disposed within the first region and configured to heat the first region to the first temperature, and (b) a second coil disposed within the second region and configured to heat the second region to the second temperature.

Abstract: A semiconductor device includes a memory region, a plurality of bit lines in the memory region, a first low-k dielectric layer on each sidewall of each bit line, a plurality of storage node regions between the bit lines, and a second low-k dielectric layer surrounding each storage node region.

Abstract: The present invention discloses a bifacial P-type PERC solar cell, which consecutively comprises a rear silver electrode, a rear aluminum grid, a rear passivation layer, P-type silicon, an N-type emitter, a front silicon nitride film, and a front silver electrode, wherein the rear silver electrode intersects with the rear aluminum grid line by a first predetermined angle, the first predetermined angle being greater than 10 degrees and smaller than 90 degrees; the rear passivation layer is grooved with laser to form a first laser grooving region, which is disposed below the rear aluminum grid line; the rear aluminum grid line is connected to the P-type silicon via the first laser grooving region and is provided at its periphery with an outer aluminum grid frame, the outer aluminum grid frame being connected to the rear aluminum grid line and the rear silver electrode. The present invention is simple in structure, low in cost, easy to popularize, and has high photoelectric conversion efficiency.

Abstract: A method of forming an n-doped organic semiconductor, the method comprising: formation of an n-dopant reagent by reaction of a composition comprising two or more precursor units for forming the n-dopant reagent and an organic semiconductor; and n-doping the organic semiconductor. One or more of the precursor units may be a substituent of a polymeric repeat unit. The n-doped organic semiconductor may be an electron-injection layer of an organic light-emitting device.