Abstract: A method for fabricating a semiconductor device comprises: providing a substrate having a top surface; forming a bottom metal embedded in the substrate; forming a first etch stop layer, a first dielectric layer, a second etch stop layer and a second dielectric layer sequentially stacked on the top surface of the substrate; forming a semiconductor element disposed on the first etch stop layer, wherein the semiconductor element comprises a top plate and an etch stop pad disposed on the top plate; performing a first etching process to form a first partial via and a second partial via penetrating the second dielectric layer, the second etch stop layer and a portion of the first dielectric layer, wherein the first partial via is separated from the bottom metal by the first dielectric layer, and the second partial via is separated from the top plate by the etch stop pad.

Abstract: Described are boron-doped amorphous carbon hard masks, methods of preparing boron-doped amorphous carbon hard masks, methods of using the boron-doped amorphous carbon hard masks, and devices that include the boron-doped amorphous carbon hard masks.

Abstract: Methods to form low-k dielectric materials for use as intermetal dielectrics in multilevel interconnect systems, along with their chemical and physical properties, are provided. The deposition techniques described include PECVD, PEALD, and ALD processes where the precursors such as TEOS and MDEOS may provide the requisite O-atoms and O2 gas may not be used as one of the reactants. The deposition techniques described further include PECVD, PEALD, and ALD processes where O2 gas may be used and, along with the O2 gas, precursors containing embedded Si—O—Si bonds, such as (CH3O)3—Si—O—Si—(CH3O)3) and (CH3)3—Si—O—Si—(CH3)3 may be used.

Abstract: Embodiments of the present disclosure generally relate to nitrogen-rich silicon nitride and methods for depositing the same, and transistors and other devices containing the same. In one or more embodiments, a passivation film stack contains a silicon oxide layer disposed on a workpiece and a nitrogen-rich silicon nitride layer disposed on the silicon oxide layer. The nitrogen-rich silicon nitride layer has a silicon concentration of about 20 at % to about 35 at %, a nitrogen concentration of about 40 at % to about 75 at %, and a hydrogen concentration of about 10 at % to about 35 at %. In one or more examples, the passivation film stack contains the silicon oxide layer, the nitrogen-rich silicon nitride layer, and a third layer containing any type of silicon nitride, such as nitrogen-rich silicon nitride and/or hydrogen-rich silicon nitride.

Abstract: The systems and methods discussed herein are for a cluster tool that can be used for MOSFET device fabrication, including NMOS and PMOS devices. The cluster tool includes process chambers for pre-cleaning, metal-silicide or metal-germanide film formation, and surface protection operations such as capping and nitridation. The cluster tool can include one or more process chambers configured to form a source and a drain. The devices fabricated in the cluster tool are fabricated to have at least one protective layer formed over the metal-silicide or metal-germanide film to protect the film from contamination during handling and transfer to separate systems.

Abstract: A method includes following steps. A semiconductor substrate is etched to form semiconductor fins. A dielectric material is deposited into a trench between the semiconductor fins. The semiconductor fins are etched such that top ends of the semiconductor fins are lower than a top surface of the dielectric material. After etching the semiconductor fins, epitaxially growing epitaxial fins on the semiconductor fins, respectively. A chemical mechanical polish (CMP) process is performed on the epitaxial fins, followed by cleaning the epitaxial fins using a non-contact-type cleaning device. The dielectric material is then such that the top surface of the dielectric material is lower than top ends of the epitaxial fins. A gate structure is formed across the epitaxial fins.

Abstract: A method for fabricating a semiconductor device includes forming a fin extending along a first direction on a semiconductor substrate and forming a sacrificial gate electrode structure extending along a second direction substantially perpendicular to the first direction over the fin. The sacrificial gate electrode structure comprises a sacrificial gate dielectric layer and a sacrificial gate electrode layer disposed over the sacrificial gate dielectric layer. Opposing gate sidewall spacers are formed extending along the second direction, on opposing sides of the sacrificial gate electrode layer. The sacrificial gate electrode layer is removed to form a gate space. Fluorine is implanted into the gate sidewall spacers after removing the gate electrode layer by performing a first fluorine implantation. The sacrificial gate dielectric layer is removed and a high-k gate dielectric layer is formed in the gate space.

Abstract: An electronic device and a method of making an electronic device. As non-limiting examples, various aspects of this disclosure provide methods of making an electronic device, and electronic devices made thereby, that comprise forming first and second encapsulating materials, followed by further processing and the removal of the entire second encapsulating material.

Abstract: To provide a laser annealing device capable of performing annealing whereby electron mobility is different depending on the part, a mask, a thin film transistor, and a laser annealing method. A laser annealing device of the present invention is provided with a mask in which a plurality of openings are formed along the scanning direction, moves a substrate in the scanning direction, and irradiates the substrate with laser light via the openings. The openings respectively have first opening regions, which are aligned in the scanning direction, and which have a same shape, and some of the openings among the openings respectively have second opening regions continuous to the first opening regions in the predetermined direction with respect to the first opening regions.

Abstract: A method for forming a 3D memory device is disclosed. The method includes: forming an alternating dielectric stack on a substrate; forming a temporary top selective gate cut in an upper portion of the alternating dielectric stack and extending along a lateral direction; forming a plurality of channel holes penetrating the alternating dielectric stack; removing the temporary top selective gate cut; and forming, simultaneously, a plurality of channel structures in the plurality of channel holes and a top selective gate cut structure.

Abstract: A layer forming method according to one embodiment of the present invention comprises: a source gas dosing/pressurizing step of dosing a source gas into a chamber having a substrate loaded therein in a state in which the outlet of the chamber is closed, thereby increasing the pressure in the chamber and adsorbing the source gas onto the substrate; a first main purging step of purging the chamber, after the source gas dosing/pressurizing step; a reactive gas dosing step of dosing a reactive gas into the chamber, after the first main purging step; and a second main purging step of purging the chamber, after the reactive gas dosing step.

Abstract: Methods of dicing semiconductor wafers, each wafer having a plurality of integrated circuits, are described. In an example, a method of dicing a semiconductor wafer having a plurality of integrated circuits involves forming a mask above the semiconductor wafer, the mask composed of a layer covering and protecting the integrated circuits. The mask is then patterned with a spatially multi-focused laser beam laser scribing process to provide a patterned mask with gaps, exposing regions of the semiconductor wafer between the integrated circuits. The semiconductor wafer is then plasma etched through the gaps in the patterned mask to singulate the integrated circuits.

Abstract: A method for fabricating a semiconductor device includes forming a fin extending along a first direction on a semiconductor substrate and forming a sacrificial gate electrode structure extending along a second direction substantially perpendicular to the first direction over the fin. The sacrificial gate electrode structure comprises a sacrificial gate dielectric layer and a sacrificial gate electrode layer disposed over the sacrificial gate dielectric layer. Opposing gate sidewall spacers are formed extending along the second direction, on opposing sides of the sacrificial gate electrode layer. The sacrificial gate electrode layer is removed to form a gate space. Fluorine is implanted into the gate sidewall spacers after removing the gate electrode layer by performing a first fluorine implantation. The sacrificial gate dielectric layer is removed and a high-k gate dielectric layer is formed in the gate space.

Abstract: A semiconductor etch process is provided in which an undercut is minimized during an etch process through tight control of etch profile, recognition of etch completion, and minimization of over etch time to increase productivity.

Abstract: Provided are a coating method, a display substrate and a manufacturing method thereof, and a display device. The coating method includes: forming a micro-fluid channel on a first surface of a first substrate, wherein the first surface is a surface to be coated of the first substrate, and a sidewall of the micro-fluid channel is the first surface of the first substrate; immersing one end of the micro-fluid channel into ink, to enable the ink to fill the micro-fluid channel; and drying the ink filling the micro-fluid channel to form a thin film on the first surface of the first substrate. The present disclosure can help implement uniform film formation of a quantum dot light-emitting layer at a high resolution, reduce the process difficulty of a high-resolution product and improve the device performance and the display performance.

Abstract: A method includes: forming source/drain epitaxy structures over a semiconductor fin; forming a first ILD layer covering the source/drain epitaxy structures; forming a gate structure over the semiconductor fin and between the source/drain epitaxy structures; forming a capping layer over the gate structure; thinning the capping layer; forming a hard mask layer over the capping layer; forming a second ILD layer spanning the hard mask layer and the first ILD layer; forming, by using an etching operation, a contact hole passing through the first and second ILD layers to one of the source/drain epitaxy structures, the etching operation being performed such that the hard mask layer has a notched corner in the contact hole; filling the contact hole with a conductive material; and performing a CMP process on the conductive material until that the notched corner of the hard mask layer is removed.

Abstract: Embodiments described herein relate to methods and materials for fabricating semiconductor device structures. In one example, a metal film stack includes a plurality of metal containing films and a plurality of metal derived films arranged in an alternating manner. In another example, a metal film stack includes a plurality of metal containing films which are modified into metal derived films. In certain embodiments, the metal film stacks are used in oxide/metal/oxide/metal (OMOM) structures for memory devices.

Abstract: A method of manufacturing a semiconductor structure includes loading the substrate from a first load lock chamber into a first processing chamber; disposing a conductive layer over the substrate in the first processing chamber; loading the substrate from the first processing chamber into the first load lock chamber; loading the substrate from the first load lock chamber into an enclosure filled with an inert gas and disposed between the first load lock chamber and a second load lock chamber; loading the substrate from the enclosure into the second load lock chamber; loading the substrate from the second load lock chamber into a second processing chamber; disposing a conductive member over the conductive layer in the second processing chamber; loading the substrate from the second processing chamber into the second load lock chamber; and loading the substrate from the second load lock chamber into a second load port.

Abstract: A display apparatus includes a substrate, a pixel defining layer, a spacer, an auxiliary electrode, and an organic light emitting diode. The substrate includes a light emitting area and a non-light emitting area adjacent to the light emitting area. The pixel defining layer is disposed on the non-light emitting area of the substrate. The spacer is disposed on the pixel defining layer. The auxiliary electrode is disposed on the spacer. The organic light emitting diode is disposed on the substrate, and at least a portion thereof is disposed in the light emitting area. The organic light emitting diode includes a pixel electrode, an intermediate layer disposed on the pixel electrode and including an organic light emitting layer, and an opposite electrode disposed on the intermediate layer and electrically connected to the auxiliary electrode.

Abstract: A method of manufacturing a semiconductor device includes forming a preliminary lower electrode layer on a substrate, the preliminary lower electrode layer including a niobium oxide; converting at least a portion of the preliminary lower electrode layer to a first lower electrode layer comprising a niobium nitride by performing a nitridation process on the preliminary lower electrode layer; forming a dielectric layer on the first lower electrode layer; and forming an upper electrode on the dielectric layer.