Abstract: The disclosure provides a method for passivating a silicon carbide epitaxial layer, relating to the technical field of semiconductors. The method includes the following steps: introducing a carbon source and a silicon source into a reaction chamber, and growing a silicon carbide epitaxial layer on a substrate; and turning off the carbon source, introducing a nitrogen source and a silicon source into the reaction chamber, and growing a silicon nitride thin film on an upper surface of the silicon carbide epitaxial layer. The silicon nitride thin film grown by the method has few defects and high quality, and may be used as a lower dielectric layer of a gate electrode in a field effect transistor. It does not additionally need an oxidation process to form a SiO2 dielectric layer, thereby reducing device fabrication procedures.

Abstract: Methods for forming a semiconductor structure including a silicon (Si) containing layer or a silicon germanium (SiGe) layer are provided. The methods include depositing a protective barrier (e.g., liner) layer over the semiconductor structure, forming a flowable dielectric layer over the liner layer, and exposing the flowable dielectric layer to high pressure steam. A cluster system includes a first deposition chamber configured to form a semiconductor structure, a second deposition chamber configured to perform a liner deposition process to form a liner layer, a third deposition chamber configured to form a flowable dielectric layer over the liner layer, an annealing chamber configured to expose the flowable oxide layer to high pressure steam.

Abstract: A semiconductor device includes channel layers disposed over a substrate, a source/drain region disposed over the substrate, a gate dielectric layer disposed on and wrapping each of the channel layers, and a gate electrode layer disposed on the gate dielectric layer and wrapping each of the channel layers. Each of the channel layers includes a semiconductor wire made of a first semiconductor material. The semiconductor wire extends into the source/drain region. The semiconductor wire in the source/drain regions is wrapped around by a second semiconductor material.

Abstract: There is provided a technique that includes forming a film on a substrate in a process chamber by performing a cycle a predetermined number of times, the cycle including non-simultaneously performing: (a) supplying a precursor gas from a first supplier to the substrate in the process chamber; and (b) supplying a reaction gas from a second supplier to the substrate in the process chamber, wherein in (a), an intermediate is generated by decomposing the precursor gas in the first supplier and in the process chamber, the intermediate is supplied to the substrate, and a decomposition amount of the precursor gas in the first supplier is set larger than a decomposition amount of the precursor gas in the process chamber.

Abstract: A method for lithography patterning includes depositing a target layer over a substrate, the target layer including an inorganic material; implanting ions into the target layer, resulting in an ion-implanted target layer; forming a photoresist layer directly over the ion-implanted target layer; and exposing the photoresist layer to radiation in a photolithography process. The ion-implanted target layer reduces reflection of the radiation back to the photoresist layer during the photolithography process.

Abstract: There is provided a technique that includes: (a) supplying aminosilane-based gas to a substrate having a surface on which first and second bases are exposed, to adsorb silicon contained in the aminosilane-based gas on a surface of one of the first and second bases; (b) supplying fluorine-containing gas to the substrate after the silicon is adsorbed on the surface of the one of the first and second bases, to react the silicon adsorbed on the surface of the one of the first and second bases with the fluorine-containing gas to modify the surface of the one of the first and second bases; and (c) supplying film-forming gas to the substrate after the surface of the one of the first and second bases is modified, to form a film on a surface of the other of the first and second bases different from the one of the first and second bases.

Abstract: The present disclosure provides a semiconductor device and a fabrication method. The method includes: providing a substrate and forming initial fins on the substrate. The initial fins include a sacrificial material layer and a first material layer on the sacrificial material layer, first trenches are formed between adjacent initial fins, and the first trenches expose the substrate. A first layer is formed in the first trenches. Second trenches are formed in the initial fins. The second trenches expose the substrate, the sacrificial material layer is formed into a sacrificial fin layer, the first material layer is formed into fins, and the fins are located on the sacrificial fin layer. The sacrificial fin layer is removed to form first fin openings between the substrate and the fins. An isolation structure is formed on the substrate and in the first fin openings.

Abstract: A semiconductor film containing silicon that is evenly doped in the semiconductor film with an enhanced semiconductor property and a method of the semiconductor film using a dopant material containing a complex compound that contains at least silicon and a halogen. The complex compound further contains a hydrocarbon group that is optionally substituted or heterocyclic group that is optionally substituted. A semiconductor film containing Si doped into the semiconductor film as a dopant to a depth that is at least 0.3 ?m or deeper from a surface of the semiconductor film is obtained by forming the semiconductor film in that the dopant material is doped, the semiconductor film is 100 ?m or less in film thickness with carrier density that is 1×1020/cm3 or less and electron mobility that is 1 cm2/Vs or more.

Abstract: There is provided a technique that includes: (a) loading a substrate into a process container; (b) heating the substrate by supplying a first gas, which is heated when passing through a first heater installed at a first gas supply line, to the substrate via a gas supplier; (c) supplying a second gas, which flows through a second gas supply line different from the first gas supply line, to the substrate mounted on a substrate mounting table in the process container, via the gas supplier; and (d) lowering a temperature of the gas supplier by supplying a third gas, which has a temperature lower than that of the first gas, to the gas supplier between (b) and (c).

Abstract: A silicon-on-insulator substrate includes: (1) a high-resistivity base layer including silicon and a trap-rich region including arsenic diffused within a first side of the high-resistivity base layer, wherein the trap-rich region has a thickness that is in a range of 1 to 10 microns and a trap density that is in a range of 0.8*1010 cm2 eV?1 to 1.2*1010 cm2 eV?1, wherein the high-resistivity base layer has resistivity in a range of 50 to 100 ohm-meters and a thickness in a range of 500 to 700 microns; (2) a silicon dioxide layer positioned on the first side of the high-resistivity base layer and having a thickness that is in a range of 1000 to 5000 angstroms; and (3) a transfer layer positioned on the silicon dioxide layer, wherein the transfer layer comprises a silicon wafer having a thickness that is a range of 500 to 5000 angstroms.

Abstract: A production of a device with superimposed levels of components including in this order providing on a given level N1 provided with one or more components produced at least partially in a first semiconductor layer: a stack including a second semiconductor layer capable of receiving at least one transistor channel of level N2, above said given level N1, the stack including a ground plane layer situated between the first and second semiconductor layers as well as an insulator layer separating the ground plane layer from the second semiconductor layer, one or more islands being defined in the second semiconductor layer. A gate is formed on at least one island. Distinct portions are etched in the second semiconductor ground plane layer. An isolation zone is formed around the island by the gate and the island.

Abstract: A method of manufacturing a trench oxide in a trench for a gate structure in a semiconductor substrate is described. The method includes: generating the trench in the semiconductor substrate; generating an oxide layer over opposing sidewalls of the trench; damaging at least a portion of the oxide layer by ion implantation; coating the oxide layer with an etching mask; generating at least one opening in the etching mask adjacent to one of the opposing sidewalls; and partly removing the oxide layer by etching the oxide layer beneath the etching mask down to an etching depth at the one of the opposing sidewalls by introducing an etching agent into the opening.

Abstract: Field-effect transistors, and apparatus including such field-effect transistors, including a gate dielectric overlying a semiconductor and a control gate overlying the gate dielectric. The control gate might include an instance of a first polycrystalline silicon-containing material containing polycrystalline silicon, and an instance of a second polycrystalline silicon-containing material containing polycrystalline silicon-germanium or polycrystalline silicon-germanium-carbon.

Abstract: A method for forming a layer comprising SiOC on a substrate is disclosed. An exemplary method includes selectively depositing a layer comprising silicon nitride on the first material relative to the second material and depositing the layer comprising SiOC overlying the layer comprising silicon nitride.

Abstract: A method of forming transistor devices includes forming a first transistor plane on a substrate, the first transistor plane including at least one layer of field effect transistors; depositing a first insulator layer on the first transistor plane; forming holes in the first insulator layer using a first etch mask; depositing a first layer of polycrystalline silicon on the first insulator layer, the first layer of polycrystalline filling the holes and covering the first insulator layer; and annealing the first layer of polycrystalline silicon using laser heating, the laser heating creating regions of single-crystal silicon. A top surface of the first transistor plane is a top surface of a stack of silicon formed by epitaxial growth.

Abstract: Embodiments described and discussed herein provide methods for depositing silicon nitride materials by vapor deposition, such as by flowable chemical vapor deposition (FCVD), as well as for utilizing new silicon-nitrogen precursors for such deposition processes. The silicon nitride materials are deposited on substrates for gap fill applications, such as filling trenches formed in the substrate surfaces. In one or more embodiments, the method for depositing a silicon nitride film includes introducing one or more silicon-nitrogen precursors and one or more plasma-activated co-reactants into a processing chamber, producing a plasma within the processing chamber, and reacting the silicon-nitrogen precursor and the plasma-activated co-reactant in the plasma to produce a flowable silicon nitride material on a substrate within the processing chamber. The method also includes treating the flowable silicon nitride material to produce a solid silicon nitride material on the substrate.

Abstract: A semiconductor device manufacturing method of an embodiment includes forming a first layer in a region of a first substrate excluding an outer peripheral portion thereof; forming a first semiconductor circuit above the first layer; forming a second semiconductor circuit on a second substrate; forming a second layer with a predetermined width at an outer peripheral portion of the second substrate; bonding a surface of the first substrate on a side provided with the first semiconductor circuit and a surface of the second substrate on a side provided with the second semiconductor circuit; and applying tensile stress to the first layer and the second layer to debond the first layer and the second layer, thereby forming the second substrate including the first semiconductor circuit and the second semiconductor circuit.

Abstract: A method and apparatus for forming a backside coating on a substrate to counteract stresses from a previously deposited film is disclosed. In one embodiment, a method for flattening a bowed substrate includes providing a substrate having a film stack formed on a first major surface thereof, wherein the substrate comprises a bowed orientation, and forming a coating a second major surface of the substrate, wherein the coating is configured to counter stresses produced by the film stack and flattens the substrate from the bowed orientation.

Abstract: A light-emitting panel and its manufacturing method are provided. The light-emitting panel includes a backboard, an electroluminescence device and an adhesive layer that are sequentially laminated; the light-emitting panel further includes a convex lens array, which includes a plurality of convex lenses on a side of the adhesive layer close to the electroluminescence device. A light-emitting surface of the electroluminescence device faces the adhesive layer, and the plurality of convex lenses included by the convex lens array protrude toward the adhesive layer.

Abstract: A method for preparation of orientation-patterned (OP) templates comprising the steps of: depositing a first layer of a first material on a common substrate by a far-from-equilibrium process; and depositing a first layer of a second material on the first layer of the first material by a close-to-equilibrium process, wherein a first assembly is formed. The first material and the second material may be the same material or different materials. The substrate material may be Al2O3 (sapphire), silicon (Si), germanium (Ge), GaAs, GaP, GaSb, InAs, InP, CdTe, CdS, CdSe, or GaSe. The first material deposited on the common substrate may be one or more electronic or optical binary materials from the group consisting of AlN, GaN, GaP, InP, GaAs, InAs, AlAs, ZnSe, GaSe, ZnTe, CdTe, HgTe, GaSb, SiC, CdS, CdSe, or their ternaries or quaternaries. The far-from-equilibrium process is one of MOCVD and MBE, and the close-to-equilibrium process is HVPE.