Abstract: A semiconductor device manufacturing method of an embodiment includes forming a first layer in a region of a first substrate excluding an outer peripheral portion thereof; forming a first semiconductor circuit above the first layer; forming a second semiconductor circuit on a second substrate; forming a second layer with a predetermined width at an outer peripheral portion of the second substrate; bonding a surface of the first substrate on a side provided with the first semiconductor circuit and a surface of the second substrate on a side provided with the second semiconductor circuit; and applying tensile stress to the first layer and the second layer to debond the first layer and the second layer, thereby forming the second substrate including the first semiconductor circuit and the second semiconductor circuit.

Abstract: A method and apparatus for forming a backside coating on a substrate to counteract stresses from a previously deposited film is disclosed. In one embodiment, a method for flattening a bowed substrate includes providing a substrate having a film stack formed on a first major surface thereof, wherein the substrate comprises a bowed orientation, and forming a coating a second major surface of the substrate, wherein the coating is configured to counter stresses produced by the film stack and flattens the substrate from the bowed orientation.

Abstract: A light-emitting panel and its manufacturing method are provided. The light-emitting panel includes a backboard, an electroluminescence device and an adhesive layer that are sequentially laminated; the light-emitting panel further includes a convex lens array, which includes a plurality of convex lenses on a side of the adhesive layer close to the electroluminescence device. A light-emitting surface of the electroluminescence device faces the adhesive layer, and the plurality of convex lenses included by the convex lens array protrude toward the adhesive layer.

Abstract: The present disclosure provides a method and system for fabricating a semiconductor device. The method and system of the present disclosure, after obtaining the polysilicon layer, first form the protective oxide layer on the surface of the polysilicon layer, and then etch the protective oxide layer and the protrusions on the surface of the polysilicon layer with the buffered oxide etchant based on controllability of the buffered oxide etchant, thereby reducing the protrusions on the surface of the polysilicon layer, while well protecting the surface of the polysilicon layer. Therefore, the technical problem of surface roughness in the existing polysilicon layers is solved.

Abstract: A method for preparation of orientation-patterned (OP) templates comprising the steps of: depositing a first layer of a first material on a common substrate by a far-from-equilibrium process; and depositing a first layer of a second material on the first layer of the first material by a close-to-equilibrium process, wherein a first assembly is formed. The first material and the second material may be the same material or different materials. The substrate material may be Al2O3 (sapphire), silicon (Si), germanium (Ge), GaAs, GaP, GaSb, InAs, InP, CdTe, CdS, CdSe, or GaSe. The first material deposited on the common substrate may be one or more electronic or optical binary materials from the group consisting of AlN, GaN, GaP, InP, GaAs, InAs, AlAs, ZnSe, GaSe, ZnTe, CdTe, HgTe, GaSb, SiC, CdS, CdSe, or their ternaries or quaternaries. The far-from-equilibrium process is one of MOCVD and MBE, and the close-to-equilibrium process is HVPE.

Abstract: A method for fabricating high electron mobility transistor (HEMT) includes the steps of: forming a buffer layer on a substrate; forming a barrier layer on the buffer layer; forming a hard mask on the barrier layer; removing the hard mask to form a first recess for exposing the barrier layer; removing the hard mask adjacent to the first recess to form a second recess; and forming a p-type semiconductor layer in the first recess and the second recess.

Abstract: A method of forming an oxide film including two non-oxygen elements includes providing a first source material on a substrate, the first source material including a first central element, providing an electron donor compound to be bonded to the first source material, providing a second source material on the substrate after the providing of the electron donor compound, the second source material including a second central element, and providing an oxidant on the substrate.

Abstract: A method is provided for producing a microelectronic component on a substrate including in an exposed manner on a first face thereof, an active zone and an electrical isolation zone adjacent thereto, the method including forming a gate on the active zone, forming spacers each configured to cover a surface of a different edge of the gate, and forming source and drain zones by doping portions of the active zone adjacent to the gate, the method successively including forming a first layer of spacer material above the active zone and the electrical isolation zone; an ion implantation to produce doping of the portions through the first layer; removing a modified portion of the first layer disposed overlooking the portions, the modified portion coming from the ion implantation, the removing being configured to preserve at least part of the first layer at a level of edges of the gate.

Abstract: A support including a heat resistant film layer and a resin layer, wherein the heat resistant film layer is laminated on at least one side (a first side) of the resin layer, and the resin layer is in a semi-cured state (B stage).

Abstract: A method of manufacturing a semiconductor device, the method including providing a metal precursor on a substrate to form a preliminary layer that includes a first metal; providing a reducing agent on the preliminary layer, the reducing agent including a compound that includes a second metal; and providing a reactant on the preliminary layer to form a metal-containing layer, wherein the second metal has multiple oxidation states, the second metal in the reducing agent having a lower oxidation state among the multiple oxidation states prior to providing the reducing agent on the preliminary layer.

Abstract: A method for forming a gate stack of a field-effect transistor includes depositing a Si capping layer on a Ge channel material (100). The method further includes depositing an oxide layer on the Si capping layer by a plasma enhanced deposition technique at a temperature less than or equal to 200° C., and a plasma power less than or equal to 100 W.

Abstract: There is provided a technique which includes (a) forming a seed layer on a substrate by supplying a first process gas to the substrate at a first temperature, (b) forming a film on the seed layer by supplying a second process gas to the substrate at a second temperature, and (c) annealing the seed layer and the film at a third temperature, wherein at least one selected from the group of a crystal grain size and a surface roughness of the film after performing the annealing in (c) is adjusted by controlling a thickness of the seed layer formed in (a).

Abstract: A method of delidding an integrated circuit (IC) package includes directing a laser beam along a cut line of an integrated circuit package. The cut line defines a removable portion, the cutting occurs along the cut line, and the removable portion is removed after the directing. A method of troubleshooting an integrated circuit package is also disclosed.

Abstract: A plurality of endpoints in a wet etching process of a substrate are determined. A plurality of benchmark end points during a wet etching process of a first substrate are determined, using first light information represented by a HSV color model for sample locations of the first substrate. Etch parameters are generated for a wet etching process for a second substrate. The generated etch parameters are used with second light information represented by at least one value of the Hue, Saturation, Value color model associated with a plurality of sample locations of the second substrate to reach respective end points during the wet etching process of a second substrate.

Abstract: Disclosed herein is an apparatus comprising: an X-ray absorption layer; a first electrical contact and a second electrical contact; wherein the first electrical contact and the second electrical contact respectively comprise structures extending into the X-ray absorption layer; wherein the structures of the first electrical contact and the structures of the second electrical contact do not electrically short.

Abstract: Embodiments of the present technology may include a method of forming a stack of semiconductor layers. The method may include depositing a first silicon oxide layer on a substrate. The method may also include depositing a first silicon layer on the first silicon oxide layer. The method may include depositing a first silicon nitride layer on the first silicon layer. The method may further include depositing a second silicon layer on the first silicon nitride layer. In addition, the method may include depositing a stress layer on a side of the substrate opposite a side of the substrate with the first silicon oxide layer. The operations may form a structure of semiconductor layers, where the structure includes the first silicon oxide layer, the first silicon layer, the first silicon nitride layer, the second silicon layer, the substrate, and the stress layer. Other methods of reducing stress are described.

Abstract: A method for printing a semiconductor material includes depositing a molten metal onto a substrate in an enclosed chamber to form a trace having a maximum height of 15 micrometers, a maximum width of 25 micrometers to 10 millimeters, and/or a thin film having a maximum height of 15 micrometers. The method further includes reacting the molten metal with a gas phase species in the enclosed chamber to form the semiconductor material.

Abstract: A fine metal mask (100) comprising a pattern region (110) comprising a plurality of openings; and a plurality of alignment holes (120) located outside the pattern region (110). Also disclosed are a display substrate (200) and an alignment method for the fine metal mask (100) for evaporation.

Abstract: A method for fabricating a semiconductor device comprises: providing a substrate having a top surface; forming a bottom metal embedded in the substrate; forming a first etch stop layer, a first dielectric layer, a second etch stop layer and a second dielectric layer sequentially stacked on the top surface of the substrate; forming a semiconductor element disposed on the first etch stop layer, wherein the semiconductor element comprises a top plate and an etch stop pad disposed on the top plate; performing a first etching process to form a first partial via and a second partial via penetrating the second dielectric layer, the second etch stop layer and a portion of the first dielectric layer, wherein the first partial via is separated from the bottom metal by the first dielectric layer, and the second partial via is separated from the top plate by the etch stop pad.

Abstract: Described are boron-doped amorphous carbon hard masks, methods of preparing boron-doped amorphous carbon hard masks, methods of using the boron-doped amorphous carbon hard masks, and devices that include the boron-doped amorphous carbon hard masks.