Abstract: Embodiments described herein relate to methods and materials for fabricating semiconductor device structures. In one example, a metal film stack includes a plurality of metal containing films and a plurality of metal derived films arranged in an alternating manner. In another example, a metal film stack includes a plurality of metal containing films which are modified into metal derived films. In certain embodiments, the metal film stacks are used in oxide/metal/oxide/metal (OMOM) structures for memory devices.

Abstract: A method of manufacturing a semiconductor structure includes loading the substrate from a first load lock chamber into a first processing chamber; disposing a conductive layer over the substrate in the first processing chamber; loading the substrate from the first processing chamber into the first load lock chamber; loading the substrate from the first load lock chamber into an enclosure filled with an inert gas and disposed between the first load lock chamber and a second load lock chamber; loading the substrate from the enclosure into the second load lock chamber; loading the substrate from the second load lock chamber into a second processing chamber; disposing a conductive member over the conductive layer in the second processing chamber; loading the substrate from the second processing chamber into the second load lock chamber; and loading the substrate from the second load lock chamber into a second load port.

Abstract: A display apparatus includes a substrate, a pixel defining layer, a spacer, an auxiliary electrode, and an organic light emitting diode. The substrate includes a light emitting area and a non-light emitting area adjacent to the light emitting area. The pixel defining layer is disposed on the non-light emitting area of the substrate. The spacer is disposed on the pixel defining layer. The auxiliary electrode is disposed on the spacer. The organic light emitting diode is disposed on the substrate, and at least a portion thereof is disposed in the light emitting area. The organic light emitting diode includes a pixel electrode, an intermediate layer disposed on the pixel electrode and including an organic light emitting layer, and an opposite electrode disposed on the intermediate layer and electrically connected to the auxiliary electrode.

Abstract: A method of manufacturing a semiconductor device includes forming a preliminary lower electrode layer on a substrate, the preliminary lower electrode layer including a niobium oxide; converting at least a portion of the preliminary lower electrode layer to a first lower electrode layer comprising a niobium nitride by performing a nitridation process on the preliminary lower electrode layer; forming a dielectric layer on the first lower electrode layer; and forming an upper electrode on the dielectric layer.

Abstract: Disclosed is an oxide film formation method that includes supplying an ozone gas having an ozone concentration of 20 to 100 vol %, an unsaturated hydrocarbon gas and a raw material gas to a workpiece (7) placed in a pressure-reduced treatment furnace (5), whereby an oxide film is formed on a surface of the workpiece (7) by a chemical vapor deposition process. An example of the unsaturated hydrocarbon gas is an ethylene gas. An example of the raw material gas is a TEOS gas. The flow rate of the ozone gas is preferably set equal to or more than twice the total flow rate of the unsaturated hydrocarbon gas and the raw material gas. By this oxide film formation method, the oxide film is formed on the workpiece (7) at a high deposition rate even under low-temperature conditions of 200° C. or lower.

Abstract: A multi integrated circuit (IC) chip package includes multiple IC chips, a carrier, and a lid. The IC chips may be connected to the carrier. Alternatively, each IC chip may be connected to an interposer and multiple interposers may be connected to the carrier. The carrier may be positioned against a carrier deck. The lid may be positioned relative to carrier by aligning one or more alignment features within the lid with one or more respective alignment features of the carrier deck. A compression fixture cover may contact the lid and exert a force toward the carrier deck, the lid be loaded against respective IC chips, and the lid may be loaded against the carrier. While under compression, thermal interface material between respective the lid and respective IC chips and seal band material between the lid and the carrier may be cured.

Abstract: An oxide semiconductor device has an improved withstand voltage when an inverse voltage is applied, while suppressing diffusion of different types of materials to a Schottky interface. The oxide semiconductor device includes an n-type gallium oxide epitaxial layer, p-type oxide semiconductor layers of an oxide that is a different material from the material for the gallium oxide epitaxial layer, a dielectric layer formed to cover at least part of a side surface of the oxide semiconductor layer, an anode electrode, and a cathode electrode. Hetero pn junctions are formed between the lower surfaces of the oxide semiconductor layers and a gallium oxide substrate or between the lower surfaces of the oxide semiconductor layers and the gallium oxide epitaxial layer.

Abstract: An apparatus includes a transfer substrate with two or more transfer elements. Each of the transfer elements includes an adhesion element having a first surface adhesion at a first temperature and a second surface adhesion at a second temperature. The second surface adhesion less than the first surface adhesion. Each transfer element has a thermal element operable to change a temperature of the adhesion element in response to an input. A controller is coupled to provide the inputs to the thermal elements of the two or more transfer elements to cause a subset of the transfer elements to selectably hold objects to and release the objects from the transfer substrate in response to changes between the first and second surface adhesion of the subset of the transfer elements.

Abstract: A solar cell module comprises a plate-like first protector having translucency, a second protector, a solar cell element, first to third sealers, and first and second wiring members. The solar cell element is located between the first protector and the second protector. The first sealer covers the solar cell element from a side of the first protector between the first protector and the solar cell element. The second sealer covers the solar cell element from a side of the second protector between the solar cell element and the second protector. The third sealer covers the second sealer from a side of the second protector between the second sealer and the second protector. The first wiring member is electrically connected to the solar cell element and passes through the second sealer. The second wiring member is connected to the first wiring member between the second sealer and the second protector.

Abstract: An ion depth profile control method includes performing reinforcement learning, whereby a similarity between an ion depth profile and a box profile is output as a reward when the similarity is equal to or greater than a set criterion, the ion depth profile being an ion concentration according to a wafer depth in an ion implantation process, and the box profile being a target profile, obtaining at least one process condition of the ion implantation process as a result of the reinforcement learning, and generating a process recipe regarding the at least one process condition.

Abstract: A method of forming a semiconductor structure includes providing a substrate; forming a low-k dielectric layer over the substrate; embedding a conductive wiring into the low-k dielectric layer; and thermal soaking the conductive wiring in a carbon-containing silane-based chemical to form a barrier layer on the conductive wiring. A lining barrier layer is formed in the opening for embedding the conductive wiring. The lining barrier layer may comprise same materials as the barrier layer, and the lining barrier layer may be recessed before forming the barrier layer and may contain a metal that can be silicided.

Abstract: A process includes the following successive steps: a) providing a substrate including a structured first electrode; b) forming in succession first and second bilayer stacks on the structured first electrode, each bilayer stack including in succession first and second layers made of first and second materials that are transparent conductive oxides able to be selectively etched; c) etching the second bilayer stack in a zone intended to accommodate a blue subpixel and in a zone intended to accommodate a green subpixel; d) etching the first bilayer stack in the zone intended to accommodate the blue subpixel; e) forming a stack of organic light-emitting layers, the stack being configured to emit white light; f) forming a second electrode on the stack of organic light-emitting layers so as to obtain an optical resonator with the first electrode.

Abstract: A method of forming an integrated circuit structure includes forming a first source/drain contact plug over and electrically coupling to a source/drain region of a transistor, forming a first dielectric hard mask overlapping a gate stack, recessing the first source/drain contact plug to form a first recess, forming a second dielectric hard mask in the first recess, recessing an inter-layer dielectric layer to form a second recess, and forming a third dielectric hard mask in the second recess. The third dielectric hard mask contacts both the first dielectric hard mask and the second dielectric hard mask.

Abstract: Disclosed are methods of forming devices. One method may include providing a first set of fins and a second set of fins extending from a substrate, and providing a dummy oxide over the first set of fins and the second set of fins. The method may further include performing a thermal implant to the second set of fins, wherein the thermal implant is an angled ion implant impacting the dummy oxide. The method may further include removing the dummy oxide from the first set of fins and the second set of fins, and forming a first work function (WF) metal over the first set of fins and a second WF metal over the second set of fins.

Abstract: A method includes a step of forming a plurality of semiconductor devices having active regions, in a wafer, a step of forming a plurality of cleavage grooves on an upper surface side of the wafer, and a step of cleaving the wafer from the upper surface side of the wafer to expose steps formed by the plurality of cleavage grooves, and the plurality of active regions, on a sectional surface, wherein the active region is provided in a semicircle that has a radius that is a distance from a bottom of the cleavage groove to a lower surface of the wafer, and has a center that is on the lower surface of the wafer and is immediately below the cleavage groove in a cleavage propagation direction.

Abstract: There is provided a technique that includes: (a) forming a first film including a cyclic structure composed of silicon and carbon and also including nitrogen so as to fill a recess formed in a surface of a substrate by performing a cycle a predetermined number of times, the cycle including non-simultaneously performing: supplying a precursor including the cyclic structure and also including halogen to the substrate having the recess formed on its surface; and supplying a nitriding agent to the substrate; (b) converting the first film into a second film including the cyclic structure and also including oxygen by supplying a first oxidizing agent to the substrate; and (c) converting the second film into a third film including silicon and oxygen and not including carbon and nitrogen by supplying a second oxidizing agent to the substrate.

Abstract: The invention relates to a method for producing a plurality of components (100), wherein a carrier composite (10) is provided with a coherent base body (13) and a wafer composite (200) is provided with a coherent semiconductor body composite (20) and a substrate (9). The wafer composite is connected to the carrier composite to form a common composite. In a subsequent method step, a plurality of separation channels (60) are generated at least through the base body (13) to form a grid structure (6), which determines the dimensions of the components (100) to be produced. A passivation layer (61) is shaped in such a way that it covers the side surfaces of the separation channels (60). Finally, the common composite is separated, wherein the substrate (9) is removed from the semiconductor body composite (20) and the common composite is separated along the separation channels (60) to form a plurality of components (100).

Abstract: An organic light emitting diode (OLED) display panel includes a display area, and the display area includes: a light transmissive zone; a display zone surrounding the light transmissive zone; and a common layer disposed on the display zone; the common layer includes an organic electroluminescence device and a thin film encapsulation layer, and there is no common layer disposed on the light transmissive zone.

Abstract: A selective modification method of a base material surface includes subjecting at least a part of a surface of a base material to at least one surface treatment selected from the group consisting of an oxidization treatment and a hydrophilization treatment. The base material includes a surface layer and includes an oxide, a nitride or an oxynitride of silicon, or a combination thereof in a first region of the surface layer. A nonphotosensitive composition is applied directly or indirectly on the surface of the base material after the surface treatment. The nonphotosensitive composition includes: a first polymer containing a nitrogen atom; and a solvent. It is preferred that the base material contains a metal in a second region which is other than the first region of the surface layer. In the surface treatment step, an O2 plasma treatment is preferably conducted.

Abstract: The present invention relates to a process of forming electrical conductor on a substrate comprising the steps of a) providing a substrate; b) providing an electrically conductive composition; c) applying said electrically conductive composition to at least one part of said substrate; and d) exposing said electrically conductive composition on the substrate to a near infrared light to form an electrical conductor. NIR light cure provides improved electrical properties of the cured composition without damaging heat sensitive substrates.