Abstract: Embodiments herein include void-free material depositions on a substrate (e.g., in a void-free trench-filled (VFTF) component). In some embodiments, a method may include providing a plurality of device structures extending from a base, each of the plurality of device structures including a first sidewall opposite a second sidewall and a top surface extending between the first and second sidewalls, and providing a seed layer over the plurality of device structures. The method may further include forming a dielectric layer along just the top surface and along an upper portion of the first and second sidewalls using an angled deposition delivered to the plurality of device structures at a non-zero angle of inclination relative to a perpendicular extending from an upper surface of the base, and forming a fill material within one or more trenches defined by the plurality of device structures.

Abstract: A flow meter, and related system and method are provided. The flow meter includes a coupler, a support member, an image sensor, a valve, and one or more processors. The coupler is adapted to couple to a drip chamber. The support member is operatively coupled to the coupler. The image sensor has a field of view and is operatively coupled to the support member. The image sensor is positioned to view the drip chamber within the field of view. The one or more processors are operatively coupled to the image sensor to receive image data therefrom and to the actuator to actuate the valve. The one or more processors are configured to estimate a flow of fluid through the drip chamber and to actuate the valve to control the flow of fluid through the drip chamber to achieve a target flow rate.

Abstract: To manufacture an integrated circuit (IC) device, a lower structure having a step structure defining a trench is prepared. A material film is formed inside the trench. To form a material film, a first precursor including a first central element and a first ligand having a first size is supplied onto a lower structure to form a first chemisorbed layer of the first precursor on the lower structure. A second precursor including a second central element and a second ligand having a second size less than the first size is supplied onto a resultant structure including the first chemisorbed layer to form a second chemisorbed layer of the second precursor on the lower structure. A reactive gas is supplied to the first chemisorbed layer and the second chemisorbed layer.

Abstract: In an embodiment, a method of manufacturing a semiconductor device includes preparing a deposition processing chamber by flowing first precursors to form a dielectric coat along an inner sidewall of the deposition processing chamber and flowing a second precursor to form a hydrophobic layer over the dielectric coat. In addition one or more deposition cycles are performed. Next, the second precursor is flowed again to repair the hydrophobic layer.

Abstract: Systems and methods of using pulsed RF plasma to form amorphous and microcrystalline films are discussed herein. Methods of forming films can include (a) forming a plasma in a process chamber from a film precursor and (b) pulsing an RF power source to cause a duty cycle on time (TON) of a duty cycle of a pulse generated by the RF power source to be less than about 20% of a total cycle time (TTOT) of the duty cycle to form the film. The methods can further include (c) depositing a first film interlayer on a substrate in the process chamber; (d) subsequent to (c), purging the process chamber; and (e) subsequent to (d), introducing a hydrogen plasma to the process chamber. Further in the method, (b)-(e) are repeated to form a film. The film can have an in-film hydrogen content of less than about 10%.

Abstract: Disclosed herein is a high throughput method for providing directional protection to a three dimensional feature on a substrate by forming a multi-layer amorphous carbon-containing coating with tunable conformality thereon. Forming the multi-layer amorphous carbon-containing coating with tunable conformality includes depositing a base layer onto a horizontal surface of the three dimensional features, and a second layer over the base layer and onto a first portion of a vertical or inclined surface of the three dimensional feature. The base layer includes a first material with a first sticking coefficient and the second layer includes a second material with a second sticking coefficient that is smaller than the first sticking coefficient. The first material includes no fluorine or less fluorine than the second material. Also disclosed herein is a method of manufacturing a three dimensional device as well as three dimensional devices.

Abstract: There is included (a) forming a film on a substrate by supplying a first processing gas to the substrate in a process container; (b) forming a first pre-coated film, which has a first thickness and has a material different from a material of the film formed in (a), in the process container by supplying a second processing gas into the process container in a state in which the substrate does not exist in the process container; and (c) forming a second pre-coated film, which has a second thickness smaller than the first thickness and has the same material as the material of the film formed in (a), on the first pre-coated film formed in the process container by supplying a third processing gas into the process container in the state in which the substrate does not exist in the process container.

Abstract: Methods and systems for forming complex oxide films are provided. Also provided are complex oxide films and heterostructures made using the methods and electronic devices incorporating the complex oxide films and heterostructures. In the methods pulsed laser deposition is conducted in an atmosphere containing a metal-organic precursor to form highly stoichiometric complex oxides.

Abstract: A method for selectively depositing silicon nitride on a first material relative to a second material is disclosed. An exemplary method includes treating the first material, and then selectively depositing a layer comprising silicon nitride on the second material relative to the first material. Exemplary methods can further include treating the deposited silicon nitride.

Abstract: Pixelated-LED chips and related methods are disclosed. A pixelated-LED chip includes an active layer with independently electrically accessible active layer portions arranged on or over a light-transmissive substrate. The active layer portions are configured to illuminate different light-transmissive substrate portions to form pixels. Various enhancements may beneficially provide increased contrast (i.e., reduced cross-talk between pixels) and/or promote inter-pixel illumination homogeneity, without unduly restricting light utilization efficiency. In some aspects, a light extraction surface of each substrate portion includes protruding features and light extraction surface recesses. Lateral borders between different pixels are aligned with selected light extraction surface recesses. In some aspects, selected light extraction surface recesses extend through an entire thickness of the substrate. Other technical benefits may additionally or alternatively be achieved.

Abstract: There is provided a film forming method, including: forming a film containing silicon, carbon and nitrogen on a substrate in a first process; and oxidizing the film with an oxidizing agent containing a hydroxy group and subsequently supplying a nitriding gas to the substrate in a second process.

Abstract: A method for growing a GaN crystal suitable as a material of GaN substrates including C-plane GaN substrates includes: a first step of preparing a GaN seed having a nitrogen polar surface; a second step of arranging a pattern mask on the nitrogen polar surface of the GaN seed, the pattern mask being provided with a periodical opening pattern comprising linear openings and including intersections, the pattern mask being arranged such that longitudinal directions of at least part of the linear openings are within ±3° from a direction of an intersection line between the nitrogen polar surface and an M-plane; and a third step of ammonothermally growing a GaN crystal through the pattern mask such that a gap is formed between the GaN crystal and the pattern mask.

Abstract: A method for manufacturing a CMOS device includes: forming a gate structure and gate sidewalls of the CMOS device, wherein the material of the gate sidewalls is silicon nitride; depositing a silicon nitride film directly on the gate structure and the gate sidewalls, wherein the depositing is performed via atomic layer deposition (ALD); and performing a photolithography process to define an ion implantation region.

Abstract: Methods for deposition of high-hardness low-? dielectric films are described. More particularly, a method of processing a substrate is provided. The method includes flowing a precursor-containing gas mixture into a processing volume of a processing chamber having a substrate, the precursor having the general formula (I) wherein R1, R2, R3, R4, R5, R6, R7, and R8 are independently selected from hydrogen (H), alkyl, alkoxy, vinyl, silane, amine, or halide; maintaining the substrate at a pressure in a range of about 0.1 mTorr and about 10 Torr and at a temperature in a range of about 200° C. to about 500° C.; and generating a plasma at a substrate level to deposit a dielectric film on the substrate.

Abstract: A deposition method includes a first process performed by repeating causing aminosilane gas to be adsorbed on a substrate; causing a first silicon oxide film to be stacked on the substrate by supplying oxidation gas to the substrate to oxidize the aminosilane gas adsorbed on the substrate; and performing a reforming process on the first silicon oxide film by activating a first reformed gas by plasma and supplying the first reformed gas to the first silicon oxide film, and a second process, performed after the first process, by repeating causing aminosilane gas to be adsorbed on the substrate; causing a second silicon oxide film to be stacked on the substrate by supplying oxidation gas; and performing a reforming process on the second silicon oxide film by supplying a plasma-activated second reformed gas. The first reformed gas has a smaller effect of oxidizing the substrate than the second reformed gas.

Abstract: A method for forming spacers on a gate pattern includes deposition of a first dielectric layer having basal portions on an active layer and side portions of the edges of the pattern; anisotropic modification of only the basal portions of the first layer, so as to obtain modified basal portions; deposition of a second dielectric layer on the first layer, also having basal and side portions; anisotropic etching of only the basal portions of the second layer, so as to remove these basal portions while conserving the side portions; and removal of the modified basal portions while conserving the first and second non-modified side portions, by selective etching of the modified dielectric material vis-à-vis the non-modified dielectric material.

Abstract: The present disclosure provides a method that includes receiving a semiconductor substrate that includes an integrated circuit (IC) cell and a well tap cell surrounding the IC cell; forming first fin active regions in the well tap cell and second fin active regions in the IC cell; forming a hard mask within the well tap cell, wherein the hard mask includes openings that define first source/drain (S/D) regions on the first fin active region of the well tap cell; forming gate stacks on the second fin active regions within the IC cell and absent from the well tap cell, wherein the gate stacks define second S/D regions on the second fin active regions; epitaxially growing first S/D features in the first S/D regions using the hard mask to constrain the epitaxially growing; and forming contacts landing on the first S/D features within the well tap cell.

Abstract: A high-k dielectric layer is formed over a semiconductor substrate having a first trench and a second trench. A barrier layer is formed over the high-k dielectric layer. A work function layer is deposited over the barrier layer, and is patterned and removed from the second trench, exposing the barrier layer at the second trench. A precursor is deposited selectively over the barrier layer in the second trench, and deposited over the work function layer in the first trench. The precursor selectively reacts with the barrier layer to selectively etch the barrier layer, and selectively reacts with the work function layer to selectively etch a top oxidized portion of the work function layer and deposit a protective layer. The reaction products between the precursor and the barrier layer, and the reaction products between the precursor and the work function layer are removed by using an inert gas.

Abstract: Methods for plasma enhanced atomic layer deposition (PEALD) of low-K films are described. A method of depositing a film comprises exposing a substrate to a silicon precursor having the general formula (I) wherein R1, R2, R3, R4, R5, and R6 are independently selected from hydrogen (H), substituted alkyl, or unsubstituted alkyl; purging the processing chamber of the silicon precursor; exposing the substrate to a carbon monoxide (CO) plasma to form one or more of a silicon oxycarbide (SiOC) or silicon oxycarbonitride (SiOCN) film on the substrate; and purging the processing chamber.

Abstract: A technique comprising: providing an assembly temporarily adhered on opposite sides to respective carriers by respective adhesive elements, the assembly including at least one plastic support sheet; heating the assembly while mechanically compressing the assembly between the carriers, wherein the strength of adhesion of one of said adhesive elements to the respective carrier and/or to the assembly is partially reduced during said heating of the assembly under mechanical compression; and wherein the strength of adhesion of the said adhesive element to the carrier and/or to the assembly is further reducible by further heating the said adhesive element after partially or completely relaxing the pressure at which the assembly is mechanically compressed between the two carriers.