Abstract: A bus architecture is disclosed that provides for transaction queue reallocation on the modules communicating using the bus. A module can implement a transaction request queue by virtue of digital electronic circuitry, e.g., hardware or software or a combination of both. Some bus clogging issues that affect conventional systems can be circumvented by combining an out of order system bus protocol that uses a transaction request replay mechanism. Modules can evict less urgent transactions from transaction request queues to make room to insert more urgent transactions. Master modules can dynamically update a quality of service (QoS) value for a transaction while the transaction is still pending.

Abstract: This system on chip comprises a plurality of master resources, a plurality of slave resources, a plurality of arbitration levels, each arbitration level being able to control the access of at least one master resource to at least one slave resource, each master resource being able to send requests to at least one slave resource according to a bandwidth associated with this slave resource and this master resource. The system is characterized by further comprising control means configured to control each bandwidth associated with each slave resource as a function of the capacity of this slave resource to process the requests originating from the master resource corresponding to this bandwidth.

Abstract: A method and system according to embodiments enable generalized program to program interoperability. The method and system employ an automatic or substantially automatic transform adapter for using a given exchange standard for two-way communication with a program. In order for the adapter to employ the exchange standard, a discovery manager may learn the program's data communications structure and/or format, and may learn data meaning information from the program. An adapter creator may derive a transform which converts the program's data communications structure and data meaning into the exchange standard. The transform may be used by the adapter to enable two-way communication with any adapter and/or program similarly employing the given exchange standard to achieve interoperability.

Abstract: A portable storage device includes nonvolatile memory devices to store data, a storage controller, and a bridge chipset. The bridge chipset is connected to a first connector of a host through a cable assembly, detects a resistance of the cable assembly, provides the storage controller with USB type information of the first connector based on the detected resistance, and after a USB connection is established with the host, provides the storage controller with USB version information associated with the established USB connection. The storage controller selects one of a plurality of initializing modes based on the USB type information and the USB version information, selects clock signals having frequencies in a range within a maximum power level, and performs an initializing operation based on the selected clock signals within an internal reference time interval.

Abstract: A MIPI D-PHY circuit comprises a main control module, a controlled module, an internal data source generating module, and a configuration register. The main control module and the controlled module are respectively connected to the configuration register, and the main control module is connected to the internal data source generating module. The main control module and the controlled module comprise a clock channel and a data channel respectively. The clock channel and the data channel in the main control module and the data channel and the clock channel in the controlled module both comprise an error detection unit. The MIPI D-PHY circuit provided by the present disclosure adopts the error detection unit to detect the signals of the main control module and the controlled module.

Abstract: A series circuit and a computing device includes a power supply terminal, a ground terminal and a first connection line for separately connecting a first predetermined number of chips of the plurality of chips in series. A communication line is connected between adjacent chips of the first predetermined number of chips. A portion of the communication line is connected to a target connection point, which is disposed on the first connection line and adapted to the adjacent chips, via a second connection line, and the voltage at the target connection point is greater than or equal to the minimum voltage required for communication between the adjacent chips.

Abstract: Control logic within a memory control component outputs first and second memory read commands to a memory module at respective times, the memory module having memory components disposed thereon. Interface circuitry within the memory control component receives first read data concurrently from a first plurality of the memory components via a first plurality of data paths, respectively, in response to the first memory read command, and receives second read data concurrently from a second plurality of the memory components via a second plurality of data paths, respectively, in response to the second memory read command, the first plurality of the memory components including at least one memory component not included in the second plurality of the memory components and vice-versa.

Abstract: A data transmission method, including obtaining by a transmit end, at least two to-be-transmitted packets, determining a first interface used to transmit each of the packets in at least two interfaces of the transmit end, and determining an identifier of each of the packets that is related to the first interface, where the identifier represents an order of the first interface used to transmit each of the packets in the at least two interfaces used to send the at least two packets adding the identifier to a packet header of each of the packets and sending a packet added with the identifier to the receive end device through the first interface, so that the receive end device adjusts, based on the identifier, an order of the packet added with the identifier.

Abstract: According to one embodiment, an apparatus comprises a differential signaling bus, a tristate transmitter connected with the differential signaling bus, the tristate transmitter configured to provide a signal on the differential signaling bus responsive to a corresponding control signal, a receiver, a pair of differential inputs of the receiver connected with the differential signaling bus and configured to receive the signal from the differential signaling bus, and a termination circuit configured to couple a first differential input of the pair of differential inputs to a first voltage source and to couple a second differential input of the pair of differential inputs to a second voltage source, wherein the first and second voltage sources have different voltage levels.

Abstract: A system and method dynamically assign interrupts to a virtual machine from an input/output (I/O) adapter based on I/O metrics of the I/O adapter. An interrupt manager monitors I/O adapter traffic flow metrics such as latency of data transfers, usage levels, and transfers per unit of time. The interrupt manager determines when a traffic flow metric for a virtual machine meets a predetermined performance threshold and updates virtual interrupt assignments in a logical interrupt table to improve performance of the system.

Abstract: In a transfer control apparatus (100), each function unit (110) specifies a transfer time and a device ID, and makes a transfer request of device data. A first control unit (111), in response to the transfer request from a request source being any of a plurality of function units (110), transfers the device data between a first area (121) corresponding to the request source, and a second area (122) corresponding to a combination of the transfer time and the device ID specified by the request source. A second control unit (112) transfers, when a second area (122) corresponding to a transfer time being same as a time notified by a timer (113) exists, the device data between that second area (122), and a third area (123) corresponding to the same device ID as that second area (122).

Abstract: An architecture for a microcontroller includes a microcontroller, a system memory, an instruction memory, a data memory, a first bus, and a second bus, where the first and second buses perform functions of a single bus. The microcontroller connects to both buses. The instruction memory and the data memory are connected to the first bus. The system memory is connected to the second bus. The microcontroller transmits and receives data to and from the instruction memory and the data memory through the first bus. The microcontroller transmits and receives data to and from the system memory through the second bus. The instruction memory and the data memory transmit and receive data to and from the system memory through the second bus connected to the first bus, avoiding delays caused by rights and priorities and arbitration of same.

Abstract: A chip and an interface conversion device are provided. The chip includes first, second, third, fourth, fifth and sixth pads. The first and second pads are coupled to first and second SBU pins of a USB connector respectively. The fourth and the sixth pads are coupled to first and second pins of an AUX channel of a DP connector respectively. When the chip operates in a first mode, first and second AUX channel signals generated by the chip are transmitted to the third and fifth pads respectively, a voltage of the fourth pad is weakly pulled down, and a voltage of the sixth pad is weakly pulled up. When the chip operates in a second mode, one of the first and second pads is connected to the fourth pad, and the other one of the first and second pads is connected to the sixth pad.

Abstract: In an in-vehicle network, a master device and a plurality of slave devices communicate with each other. A plurality of semiconductor relays for supplying power to the corresponding slave devices is provided for each of the plurality of slave devices in the master device. IDs corresponding to the plurality of semiconductor relays are stored in a flash ROM of the master device. The master device transmits the corresponding ID each time the semiconductor relays are turned on by sequentially turning on the semiconductor relays. The plurality of slave devices set the ID received after power supply as its own ID.

Abstract: An interrupt signal is provided to a first guest operating system. A bus attachment device receives an interrupt signal from a bus connected module with an interrupt target ID identifying a processor assigned for use by the guest operating system as a target processor for handling the interrupt signal. The bus attachment device checks whether the target processor is scheduled for usage by the guest operating system. If the target processor is not scheduled for usage, the bus attachment device forwards the interrupt signal using broadcasting and updates a forwarding vector entry stored in a memory section assigned to a second guest operating system hosting the first guest operating system. The update is used for indicating to the first operating system that there is a first interrupt signal addressed to the interrupt target ID to be handled.

Abstract: Technology for detecting a capability set of a removable integrated circuit card, such as a removable memory card, is disclosed. The removable integrated circuit card has one or more capability pads that indicate a capability set of the removable integrated circuit card. The physical condition may be a physical configuration of one or more capability pads, such as size or location of a capability pad. A host device is able to determine the capability set of the removable integrated circuit card based on the physical condition of the capability pads. The host device may determine the capability set without the card being powered on, without reading a register in the card, or without exchanging commands with the card.

Abstract: Embodiments of the present invention provide an apparatus having a plurality of selectable entities having associated physical addresses, wherein the selectable entities are connected to a controller, wherein the selectable entities have a selectable processor configured to determine in response to a common control information a current select information on the basis of selectable logic combinations of a first information describing whether the selectable entity belongs to a first group and a second information describing whether the selectable entity belongs to a second group.

Abstract: According to some embodiments, an integration system may include a source data store that contains a plurality of workloads (e.g., data packets). A processing platform may retrieve a workload from the source data store via first unikernel-based workload processing. The processing platform may then process the workload (e.g., filtering or dropping) to generate an output result and arrange for the output result to be provided to a sink destination via second unikernel-based workload processing (e.g., associated with a Linux event loop model of input output multiplexing). In some embodiments, the processing platform initially evaluates the workload in the source data store to determine if the workload meets a predetermined condition. If the workload does not meet the predetermined condition, the retrieving and arranging may be performed via container-based workload processing instead of unikernel-based workload processing.

Abstract: A data communication and processing method of a master device and a slave device is provided, wherein the method includes the steps of: using the master device to transmit a frame to the slave device via a communication medium, wherein the frame includes a plurality of fields, the plurality of fields includes a bursting size field and a data field, and contents within the bursting size field indicate a data amount of the data field; and using the slave device to receive the frame and store contents of the data field, or output data to the data field according to the data amount indicated by the contents within the bursting size field of the frame. In addition, a method for replacing preamble bits with a postamble bit to improve transmission efficiency is provided.

Abstract: A system and method dynamically assign interrupts to a virtual machine from an input/output (I/O) adapter based on I/O metrics of the I/O adapter. An interrupt manager monitors I/O adapter traffic flow metrics such as latency of data transfers, usage levels, and transfers per unit of time. The interrupt manager determines when a traffic flow metric for a virtual machine meets a predetermined performance threshold and updates virtual interrupt assignments in a logical interrupt table to improve performance of the system.