Abstract: Aspects of the embodiments are directed to calibrating a cross-talk cancellation module. A data eye response for a first data channel can be acquired, and the left-side and right-side maximum transition edges can be determined while adjacent data channels are silent. The adjacent data channels can be activated, first using an even mode waveform. A strobe can be positioned at the left-side maximum boundary in anticipation of a right-shift due to even mode waveform cross talk. A summer circuit can sum the waveform from the first data channel with cross-talk induced voltage pulse having an opposite polarity from the even mode waveforms on the aggressor channels. A left-side edge can be determined by incrementally adjusting gain and detector parameters. These parameters can be locked once a left-side transition edge is located. The process can be repeated for a right-side transition edge with odd-mode aggressor waveforms.

Abstract: An adapter includes a first coupling component and a second coupling component to establish bidirectional communications between two processing devices by passing data signals through a memory card slot on one of the devices. The adapter includes a first coupling interface configured to couple with the memory card slot on a first one of the two processing devices and further includes a second coupling interface configured to couple with a second processing device. The second coupling interface is of a different form factor than the first coupling interface.

Abstract: Systems, methods, and apparatus are described. A method for data communication performed at a master device includes configuring a serial interface for a point-to-point mode of operation, transmitting a first two-bit command through the serial interface, the two-bit command including a one-bit address and a read/write bit, and initiating a transaction through the serial interface. The transaction may be identified by the two-bit command and is conducted in accordance with an I3C protocol. The transaction may include the transfer of one or more data frames formatted in accordance with the I3C protocol. The method may include receiving an acknowledgement from a slave device in response to the first two-bit command.

Abstract: Techniques are disclosed for enabling an integrated sensor hub of a main computer to access a detachable peripheral device. In an embodiment, a system includes a main unit having a peripheral interface, an embedded controller, and a device controller. The peripheral interface is configured to be detachably coupled to a peripheral. The peripheral includes a control unit and an input/output device. The embedded controller is configured to communicate with the control unit of the peripheral via the peripheral interface while the peripheral is attached to the peripheral interface. The embedded controller includes at least one data register, and in some embodiments, a set of data registers, configured to store data relating to the peripheral and to the corresponding input/output device. The device controller is configured to read data from the data register(s) of the embedded controller, write data to the data register(s) of the embedded controller, or both.

Abstract: An apparatus in one embodiment comprises a host device configured to communicate over a network with a storage system. The host device comprises a plurality of nodes each comprising a plurality of processing devices and at least one communication adapter. The host device further comprises a multi-path input-output (MPIO) driver that is configured to obtain an input-output (IO) operation that targets a given logical volume and to identify a source node for the IO operation. The MPIO driver identifies a plurality of paths between the source node and the given logical volume via the communication adapters of the plurality of nodes and determines locality information for each identified path. The MPIO driver is further configured to select a target path from the identified paths based at least in part on the determined locality information and to deliver the obtained IO operation to the given logical volume via the selected target path.

Abstract: A method includes receiving, by a storage unit of a set of storage units of a storage network, a write request of a set of write requests that includes a first group of slice payloads for first encoded data slices of each set of a plurality of sets of encoded data slices and a corresponding revision level. The method includes processing, by the storage unit, the write request by determining whether the corresponding revision level of each of the first encoded data slices is a next revision level and generating a write response message that includes a group of status messages for the first encoded data slices based on the determining whether the corresponding revision level of each of the first encoded data slices is the next revision level. The method continues by sending the write response message to a computing device of the storage network.

Abstract: A programmable arbitrary sequence direct memory access (DMA) controller accesses sequentially addressed memory locations (source or destination) using address pointer registers. Each sequentially addressed memory location containing an indirect memory address is stored in an address latch and used to access the actual non-sequential memory location to be accessed by the DMA transfer.

Abstract: An adaptable connector, a non-standard PCIe module, and a computer readable medium are disclosed. The adaptable connector for a PCIe interface allows for multiple standard PCIe modules and non-standard PCIe modules at different times An external I/O port has a set of non-PCIe I/O signal lanes coupled to the adaptable connector in lieu of a set of root port host PCIe signal lanes when a non-standard PCIe module is mated to the adaptable connector.

Abstract: A data transmission method and an apparatus used in a virtual switch technology are provided. An IO request of a virtual machine VM for accessing a file or a disk is received. When the IO request is to be sent to a physical NIC by using a user mode Open vSwitch (OVS), the IO request is converted into an Internet Small Computer Systems Interface (iSCSI) command in a user mode The iSCSI command is then sent to the user mode OVS. The user mode OVS sends the iSCSI command to the physical NIC.

Abstract: Systems, methods, and devices for monitoring operation of industrial equipment are disclosed. In one embodiment, a monitoring system is provided that includes a passive backplane and one more functional circuits that can couple to the backplane. Each of the functional circuits that are coupled to the backplane can have access to all data that is delivered to the backplane. Therefore, resources (e.g., computing power, or other functionality) from each functional circuits can be shared by all active functional circuits that are coupled to the backplane. Because resources from each of the functional circuits can be shared, and because the functional circuits can be detachably coupled to the backplane, performance of the monitoring systems can be tailored to specific applications. For example, processing power can be increased by coupling additional processing circuits to the backplane.

Abstract: The teachings of the present disclosure relate to bus systems. Various embodiments thereof may include bus coupling units, for example a bus coupler comprising: four ports comprising input/output connections to which bus cables of a two-wire bus are connectable, wherein both electrical energy and data are transmissible via both bus cables. The first port and second port are bus coupler-internally electrically conductively connectable by means of a first connection path. The third port and fourth port are bus coupler-internally electrically conductively connectable by means of a second connection path. The first connection path and second connection path are bus coupler-internally electrically conductively connectable by a bridge path.

Abstract: A network element includes one or more ports for communicating over a network, a processor and packet processing hardware. The packet processing hardware is configured to transfer packets to and from the ports, and further includes data-transfer circuitry for data transfer with the processor. The processor and the data-transfer circuitry are configured to transfer between one another (i) one or more communication packets for transferal between the ports and the processor and (ii) one or more databases for transferal between the packet processing hardware and the processor, by (i) translating, by the processor, the transferal of both the communication packets and the databases into work elements, and posting the work elements on one or more work queues in a memory of the processor, and (ii) using the data-transfer circuitry, executing the work elements so as to transfer both the communication packets and the databases.

Abstract: Systems and methods are described for modifying input and output (I/O) to an object storage service by implementing one or more owner-specified functions to I/O requests. A function can implement a data manipulation, such as filtering out sensitive data before reading or writing the data. The functions can be applied prior to implementing a request method (e.g., GET or PUT) specified within the I/O request, such that the data to which the method is applied my not match the object specified within the request. For example, a user may request to obtain (e.g., GET) a data set. The data set may be passed to a function that filters sensitive data to the data set, and the GET request method may then be applied to the output of the function. In this manner, owners of objects on an object storage service are provided with greater control of objects stored or retrieved from the service.

Abstract: A multiprocessor device includes cores and at least one ingress-write ordering circuitry (IWOC) including first and second counters associated with first and second destinations. The IWOC is configured to assign sequential numbers to write transactions received from a source, according to an order of reception at the IWOC, and to forward the write transactions from the IWOC to the first and second write-transaction destinations, while preserving the order, by incrementing the first and second counters such that both the first counter and the second counter track a sequential number of a next write transaction that the IWOC will forward, forwarding a first write transaction to the first destination only provided that the sequential number of the first write transaction matches the first counter, and forwarding a second write transaction to the second destination only provided that the sequential number of the second write transaction matches the second counter.

Abstract: Embodiments of this present disclosure may include a system that include multiple processing devices and an open ring communication bus communicatively coupled to each of the processing devices. Each processing device may use a control application to perform an operation on an industrial automation system. The control application of each processing device may output data related to the operation of the open ring communication bus during a respective timing interval used for communication via the open ring communication bus.

Abstract: A memory module comprises a data interface including a plurality of data lines and a plurality of configurable switches coupled between the data interface and a data path to one or more memories. The effective width of the memory module can be configured by enabling or disabling different subsets of the configurable switches. The configurable switches may be controlled by manual switches, by a buffer on the memory module, by an external memory controller, or by the memories on the memory module.

Abstract: One embodiment provides a computer system. The computer system comprises: a plurality of storage devices; and a first component functioning both as a network interface card and as an access switch, wherein the first component is configured to manage connections to the plurality of storage devices. A respective storage device comprises: an Ethernet port coupled to the first component; at least one microprocessor; a plurality of PCIe lanes; and a plurality of storage drives with non-volatile memory.

Abstract: Implementations of the subject matter described herein provide an input/output (I/O) card for storage device and a storage device. The I/O card and the disk drive for the storage device have the same form factor and comply with the same protocol, to enable the I/O card and the disk drive can be arranged at the same end of the storage device.

Abstract: In one embodiment, the clock management circuitry includes a first master clock controller configured to provide a first command to a first slave clock controller via a first channel based on a received first clock request. The clock management circuitry also includes the first slave clock controller configured to control outputting a first clock signal based on the first command.

Abstract: A mechanism is described for facilitating write tracking for following data eye movements across changing thermal conditions in memory systems according to one embodiment of the invention. A method of embodiments of the invention includes monitoring movements of a valid data eye associated with a memory device of a plurality of memory devices of a memory system at a computing system. The monitoring may include initiating write commands during one or more refresh periods associated with the valid data eye. The method may include determining drifting in the movement of the data eye, and correcting the drifting based on adjusting one or more existing phase interpolator values associated with the movements of the data eye.