Abstract: The present invention is directed to a system and method for tracing operations in an information handling system without changing the operating system code. Certain machine registers are shadowed during critical machine state transitions (e.g., taking and returning from interrupts), so that the tracing program does not lose control of the system. The system is interrupted before each instruction is executed, and a tracing program determines if a change in program flow has occurred. If a change in program flow has occured, a record is written to a trace log. The record contains the number of consecutive instructions executed before the program flow change, along with a displacement field indicating the number of bytes from the end of the record to the beginning of the next record. Executed instructions are also embedded in the trace log, allowing for high compression ratios and less complex post-processing of the trace data.

Abstract: A method and apparatus for emulating a dedicated terminal in semiconductor fabricator having a back end that includes a source of semiconductor substrates, a transport mechanism for transporting the substrates and a process chamber. A wall separates the back end from a front end environment. A central processing unit is provided that includes a driver for recognizing terminal text and display commands and that executes terminal text and display commands on the display screen of a terminal. A connector is provided at the back end and it is interconnected with the driver of the central processing unit. A microcomputer, that can be a laptop, personal computer or other relatively compact and portable computer is provided. This computer has a display screen and a commands entry device, such as a trackball or mouse, for manipulating commands on the display screen.

Abstract: A discreted grid producing apparatus is for discreting an analytic region into a plurality of micro-regions of discreted grid points on numerically solving a partial differential equation. The apparatus produces a discreted grid for use in obtaining simultaneous equations approximating to the partial differential equation. The apparatus comprises a grid producing section for producing grids as boundary grids on a surface and a boundary of an analytic region. The grid producing section may modifies locations of grids in order to prevent each of CV regions from passing the surface and the boundary. A basic grid producing section forms a rectangular region including the analytic region. The basic grid producing section recurrently divides the rectangular region into a plurality of micro-rectangular regions to produce basic grids. A deleting section deletes specific ones of the basic grids that exist in the analytic region.

Abstract: A data processing circuit multiplies, by 2.sup.a, input data supplied in a time-division multiplexed manner over a plurality of lines. The data processing circuit includes first, second, and third data selectors each having first, second, and third input terminals and a single output terminal. The first input terminal of the first selector is supplied with an input signal of "0". A first input line is connected in common to the second input terminal of the first data selector and the first input terminal of the second data selector. A second input line is connected in common to the third input terminal of the first data selector and the second input terminal of the second data selector. A third input line is connected in common to the third input terminal of the second data selector and the second input terminal of the third data selector.

Abstract: A circuit and method for Ethernet combination chaining of auto-negotiation sessions for multiple physical layer capability. The present invention provides control circuitry for arbitrating between different physical layer circuit types that heretofore were allowed autonomous auto-negotiation processes because only one type of physical layer circuitry was applied at each end of a communication line. The present invention operates effectively within a hub of a local area network (LAN) communication system where multiple communication standards can be employed within circuitry that communicate at different ends of a communication line, e.g., twisted pair wire. In the environment of the invention, different types of physical layer circuits are integrated within communication devices. The invention provides a mechanism whereby, at each end of the communication line, a first physical layer circuit (e.g., the master) of a first type is allowed to auto-negotiate under the IEEE 802.

Abstract: An emulator system allowing a single cycle in a system clock in a user circuit to be emulated in multiple cycles of the emulator system clock. The emulator system provides a unique architecture permitting gates in the emulator to be used to emulate functions in the user circuit without requiring a fixed correspondence between a gate in the emulator and a gate in the user circuit. The emulator system operates in synchronous and asynchronous clock modes and allows the user system clock to be stopped during emulation in selected modes while still maintaining accurate emulation.

Abstract: A system and method, operable on a general purpose computer, for debugging software that is to control a digital signal processor ("DSP") and a general purpose computer employing either the system or the method. The present invention is employable with either a real DSP or an emulated DSP.

Abstract: Disclosed is a process and apparatus for transferring data between an active file being used by an application and an external file that is stored on a storage medium. The active file will preferably have a different format than the external file. The apparatus includes a primary data structure that has plurality of standard fields and an extended field. At least some of the plurality of standard fields and the extended field are preferably associated with an element of data transferred between the active file and the external file. The primary data structure will have a directive field that is set by the application when a data transfer between the files is desired. A translator configured to extract the element of data from one of the active file and external file in response to the directive field being set by the application is provided.

Abstract: An electronic-equipment system is formed by a home switch connected to a telephone, a VCR, an audio apparatus, a-personal computer, a set-top box (decoder) and a television receiver by home data lines. The home switch transmits data received from the pieces of electronic equipment to destinations through a public data line. Before being transmitted to a destination, the data is first converted into data in a predetermined internal protocol and then converted into data in a protocol for the public data line. The home switch also receives incoming data transmitted through the public data line. The received data undergoes reversed protocol conversion before being transmitted to the electronic equipment. In addition, data output by a piece of electronic equipment can be transmitted to another piece of electronic equipment at the same home through the home switch.

Abstract: A hardware-based emulator is partitioned onto two boards. An emulation board has field-programmable gate array (FPGA) chips mounted on a top surface, and connection posts protruding through to the bottom surface. The I/O pins of the FPGA chips that carry emulated signals are connected to the connection posts but not directly to other FPGA chips on the emulation board. An interconnection board has a grid of wire-wrap posts. The tops of the wire wrap-posts mate with the connection posts when the emulation board is plugged in to the interconnection board. The wire-wrap posts extend through the interconnection board and out the bottom surface. Interconnection is made by wire-wrap wires wound around the wire-wrap posts. Thus interconnection between FPGA chips on the emulation board is made by wire-wrap on the interconnection board, while the logic gates are emulated in the FPGA chips on the separate emulation board.

Abstract: A data processing system is disclosed which includes a first processor having an m-byte data width, an n-byte data bus, where n is less than m, and a second processor electrically coupled to the bus which performs bus transactions utilizing n-byte packets of data. An adaptor is electrically coupled between the first processor and the bus which converts n-byte packets of data input from the bus to m-byte packets of data, and converts m-byte packets of data input from the first processor to n-byte packets of data, thereby enabling the first processor to transmit data to and receive data from the bus utilizing m-byte packets of data. In a second aspect of the present invention, a method and system are provided for arbitrating between two bus masters having disparate bus acquisition protocols. In response to a second bus master asserting a bus request when a first bus master controls the bus, control of the bus is removed from the first bus master.

Abstract: A system and method for processing geometry is provided which reduces the amount of memory needed for processing the geometry while improving the processing speed. The system and method deliver vertices in sequence to a vertex queue so that data in the vertex queue is freed as it is delivered and only minimal intermediate results are stored. By this incremental evaluation, less memory space is needed because input data is freed as it is used to compute results so that only small portions of intermediate results exist at any time. In another aspect of the present system and method, the vertices are maintained in the proper sequence so that sorting operations can be eliminated. More particularly, a sorted vertex queue and an unsorted vertex list are utilized so that resorting of the entire vertex list may be prevented. The use of sorted vertex queue and unsorted vertex lists are particularly useful when reading or collecting input data by allowing data to be efficiently stored and managed.

Abstract: A method for optimizing a logical design for emulation. The present invention optimzes latch-based designs by transforming them into a flip-flop based circuit. The design is analyzed to determine whether any consecutive latches are clocked by the same clock signal. If consecutive latches are clocked by the same clock signal, for example, the same phase of the same master clock, a transparency condition exists. Transparent latches are transformed into either a flip-flop/buffer/multiplexer circuit or a buffer circuit depending upon whether the latch in the logic design has an enable input. If consecutive latches in a design are clocked by different clock signals, i.e., different phases of the master clock, no transparency condition exists. Non-transparent latches are transformed into a flip-flop.

Abstract: In a multiprocessor system having a plurality of processors and main memory common to the processors, each processor includes at least one vector calculation unit which is specific to a vector calculation and which is independent of the vector calculation units in the other processors. A register holds a configuration signal representative of configuration of the vector calculation units in each processor. An access control unit controls access operations of the processors on the basis of the configuration signals in the processors to make the processors selectively access the main memory. Thus, the processors individually carry out the vector calculations to individually access the main memory.

Abstract: A local bus interface for providing high-speed data transfer between the local bus of a personal computer and one or more data storage devices. The local bus interface bypasses the standard expansion bus (ISA, EISA, Micro Channel) on the personal computer, is directly connected to the local bus, and is transparent to the system software.

Abstract: A merchandise simulator device which allows a user to operate a desired piece of merchandise on a user's terminal as if the user was using the piece actually at hand. In the merchandise simulator device, when a workstation executes merchandise simulation software received from an HTTP server, a merchandise simulation control section is activated on the workstation to thereby display the basic image of a selected piece of merchandise in a display section. If a drag operation is carried out by a mouse of an input section, then the piece of merchandise displayed on the display section is rotated on the basis of two or more pieces of image data received from the HTTP server and also, if a mouse input is given to a button or the like of the image data displayed on the display section, then the function of the piece of merchandise displayed in the display section is simulated in whatever display state the present piece is.

Abstract: The electronic circuits of a large-scale ASIC or logic device are assigned to a plurality of programmable chips with logic block division that enables the finished circuits to operate at appropriate timings. A logic division processing unit divides the electronic circuits into a plurality of groups for automatic assignment to a plurality of programmable chips. A checking unit determines whether the designated logic blocks are accommodated in one programmable chip, and a division processing unit determines which logic blocks are to be assigned and the order of assignment priorities when the designated logic blocks are not all accommodated in the same programmable chip.

Abstract: A method for reading various registers of a computer system without changing the emulator software. Address register 22, data memory I/O 30 and control register 26 surrounding D-MEM (data memory) 14 are configured as registers of a master/slave latching circuit in which serial scanning is possible, and are sequentially scanned during one scanning pass (1). Data memory I/O register 30 is connected to D-BUS (data bus) 10. External I/O registers RG1, RG2, . . . RGn are respectively connected to D-BUS (data bus) 10 and mapped in the I/O space. An IN'/OUT' instruction which can transfer data between data memory I/O register 30 and each external I/O register RG1 (i=1, 2, . . . , n) is generated.

Abstract: A configuration emulation circuit generates configuration signals to emulate a Programmable Logic Device (PLD) in a configuration timing relationship and a configuration protocol relationship between a programming circuit and the PLD. The circuit includes a first circuit to emulate the PLD in the configuration timing relationship. The circuit also includes a second circuit to emulate the PLD in the configuration protocol relationship. The second circuit is coupled to receive a configuration mode signal and is responsive to the configuration mode signal.

Abstract: A data shuffler of the pipeline type receives successive trains of n sequential data words and rearranges data words in each train according to a predetermined order. It comprises p (p.ltoreq.n) elementary processing units arranged in series. Each unit comprises an input, an output, a one-word storage register (20), a steering means (21) in order, in response to a binary control, to connect the input to the output either directly or through the register; and means for periodically supplying to each of the p steering means a sequence of n control bits determined as a function of said predetermined order.