Abstract: A method of emulating a peripheral device in a multiprocessor computer system to test device driver programs. The emulation program is loaded by a host microprocessor into one or more of the other microprocessors (target microprocessors) which are not being accessed by the operating system software. After the emulation program is loaded, control vectors to the entry point of the emulation program, where the environment in each of the target microprocessors are initialized for the emulator program. If more than one target microprocessor are utilized, then one of the target microprocessors are designated as the "master" microprocessor, which accepts interprocessor interrupts from the host microprocessor. When the device driver program running on the host microprocessor invokes an I/O command, and emulation mode is selected, then an interprocessor interrupt (IPI) is asserted to the master microprocessor.

Abstract: The present invention employs a generative approach for configuring systems such that a system may be configured based on component or resource requests, or input in the form of need. The present invention provides a constraint-based configuration system using a structural model hierarchy. The structural aspects of the model provide the ability to define a model element as being contained in, or by, another model element. In addition, the structural model provides the ability to identify logical datatype and physical interconnections between elements and establish connections between elements. To configure a system, the present invention accepts input in the form of requests (e.g., component or resource) or needs, such as an expression of a need for a desktop computer system to be used in a CAD (i.e., computer-aided design) environment.

Abstract: A timeout process circuit for performing a timeout detection process incorporated in a receiver, having a timer for incrementing time data indicating a current time, a memory including data table to store a reception time of the cell most recently received by the receiver, a register for storing a timeout value indicating a maximum permitted time interval of cell reception, a controller for reading out the reception time stored in the data table the controller receiving the timeout detection start signal from the timer, an adder for adding the reception time from the data table and the timeout value stored in the first register means, a comparator for comparing the result of the addition by the adder with the time data from the timer, and a decision circuit for receiving the comparison result from the comparator and deciding whether or not the cell of the frame in the reassembly is a timeout based on the comparison result.

Abstract: The present invention provides a cache-data transfer system improving a cache-hit rate by making a block size of the external cache memory longer than the block size of an internal cache memory. The system makes a block size of the external cache memory longer than a block size of the internal cache memory by inserting a data transfer process which transfers a data from the storage means to only the external cache memory during a data transfer process from the storage means to the internal cache memory and the external cache memory.

Abstract: A multi-processor system in wherein a plurality of processors have access to a plurality of shared memory modules, comprising a memory control unit, interconnection logic circuits, a system bus for the multipoint connection of the processors to the memory control unit and for the transfer of memory addresses and commands for ordered and successive read/write operations via the system bus and the memory control unit, whilst the transfer of data to and from the memory modules takes place through data channels which connect the various processors on a point-to-point basis to the interconnection logic circuits and via these to a memory data transfer channel.

Abstract: A method for reducing power consumed in a circuit, the circuit having at least a first and a second primary input lead, a plurality of gates, and a plurality of edges, the method includes the steps of determining a set of gates in the circuit coupled to the first primary input lead, the set of gates coupled to a set of edges, determining the 1-controllability of each edge in the set of edges; providing a binary OR tree to the circuit; coupling the set of edges to the binary OR tree; providing an AND gate to the circuit; coupling the AND gate to the binary OR tree and to the first primary input lead; providing a binary AND tree to the circuit; uncoupling the first primary input leads from the set of gates; and coupling the binary AND tree to the AND gate, to the binary OR tree, and to the set of gates.

Abstract: A power usage simulator and method for generating a baseline power usage model for a representative sample of cells in a circuit cell library, where the baseline power model is based on signal slew rates and output load for a given of environmental conditions. The baseline power usage model is aggregated for a representative set of library cells so as to provide an accurate baseline power usage computation for all logic cells rather than for each transistor or each individual cell. Thereafter, power coefficient sensitivities to varying temperature, supply voltage and process conditions are determined for each power coefficient. Power coefficient sensitivities are measured by comparing the ratios of the measured power coefficients resulting from maintaining two of the three parameters (temperature, voltage and process) at baseline values while varying the third parameter over its entire range.

Abstract: A Host Debugger and a Modular Development System (MDS) are dynamically reconfigured. The Host Debugger queries the MDS for the identity of its Target MCU. The Host Debugger receives a message containing the Target MCU identity. The corresponding Host Debug and MDS environments are then loaded based on the received Target MCU identity.

Abstract: An instruction cache for a superscalar processor having a variable byte-length instruction format, such as the X86 format, is organized as a 16K byte 4-way set-associative cache. An instruction store array is organized as 1024 blocks of 16 predecoded instruction bytes. The instruction bytes are prefetched and predecoded to facilitate the subsequent parallel decoding and mapping of up to four instructions into a sequence of one or more internal RISC-like operations (ROPs), and the parallel dispatch of up to 4 ROPs by an instruction decoder. Predecode bits are assigned to each instruction byte and are stored with the corresponding instruction byte in the instruction store array. The predecode bits include bits for identifying the starting, ending, and opcode bytes, and for specifying the number of ROPs that an instruction maps into.

Abstract: The present invention generates a model of a graded channel transistor having at least two channel portions of differing doping concentrations. The present invention assumes a uniform doping concentration of each channel portion. Each of the channel portions is modeled using a standard transistor model (100, 120) with junction voltages (64) resulting between the transistor models. The junction voltages (64) are determined to be at a level such that the channel currents of the transistor models (60, 62) are equal. Once the junction voltages (64) are determined, the parameters of the transistor models (60, 62) are determined. Once the transistor models (60, 62) are determined, the models are combined to produce a composite transistor model (70) for the transistor using standard circuit reduction techniques. The composite model produced is scalable with respect to geometry, is continuous, and is differentiable.

Abstract: A packet description language which is declarative in nature and suitable for efficiently and flexibly defining data packet formats in accordance with internetwork routing device uses. Data packet formats may be defined utilizing the packet description language and then compiled to create a data structure corresponding to the defined data packet format. A routing device test platform may generate test data packets and decode received test packets by referencing the test data to the compiled data structure defined in accordance with the packet description language. The declarative language provides for assigning numerous default values and attributes to packet fields such that only a small amount of data need be specified when regression testing a new routing device.

Abstract: A computing system architecture that uses a minimal instruction set for the functioning of a general purpose computing system as well as applying completely unencoded instructions from memory directly to the hardware is herein described. The present invention additionally uses a flowthrough design to further reduce the hardware complexity to provide a streamlined and extremely efficient architecture.

Abstract: The device is adapted more particularly to process programs written in FORTH. The device includes a) a program memory (1) storing instruction data, b) an operational unit (15) comprising a plurality of operational means (16, 17, 18), c) a central decoding unit (35), and d) a stack memory (8) for the return instructions.

Abstract: A FIFO queue is utilized to provide control information to the appropriate time slot in a time multiplexed serial link between an interface chip and a CODEC. The FIFO queue allows rewriting or replacement of any control registers present in the queue without requiring that a new entry be placed in the queue. A particular control register which is placed in the queue then maintains its place as the queue is emptied, even though the control register may be written one or more times while the control register entry is in the queue waiting for transmission to the CODEC. The loss of the prior command information is not a problem as the data rate of the serial link is still sufficiently high so that any minor transitory change which may have been desired would be of minimal effect in any regard and would have been inaudible to the human.

Abstract: A dockable computer system includes a portable computer (notebook or laptop) and a docking station (base unit). The portable computer and docking station both include a communication system so that messages can be communicated when the docking station is in an undocked state preparatory to a docked state. The communication system is preferably an infrared communication system. A communication protocol is also provided for generating an advance notice signal to warn of an impending dock. The communication protocol includes a CONNECT message, a CONNECT DETECTED message, and a CONFIRM message. Preferably, the CONNECT message is sent at a non-standard AT/PC baud rate. The communication system allows the dockable computer system to advantageously generate an advance notice signal of an impending dock and to transfer parameters necessary for the employment of sophisticated protective measures which protect the active buses of the portable computer and docking station during a docking event.

Abstract: This invention relates to personal computers, and to the handling of input/output signals exchanged between a microprocessor included within a personal computer and devices remote from the microprocessor. In addition to the microprocessor and a system board mounting the microprocessor, a personal computer in accordance with this invention has an input/output signal processing circuit for performing logical operations on digital signals passing to and from the microprocessor and preparing such signals for operative communication between the microprocessor and devices remote from the microprocessor, a second circuit board for mounting the circuit, a board connector mounting the second circuit board on the system board, an input/output connector for passing signals to and from the circuit for receipt from and delivery to devices remote from the microprocessor, and a signal communicating member extending between the circuit and the input/output connector for operatively communicating signals therebetween.

Abstract: Alternate focal bus mastering and expansion bus capability are provided for a Family I computer system where an alternate bus master and expansion or input/output bus are connectable to the computer system through a readily insertable and removable device card connected directly to the processor and memory of the computer system through a series of one or more pluggable interconnecting cards for matingly engaging a computer system planar board connector.

Abstract: A method of designing a CPU for implementation in a configurable hardware device by identifying a series of operations in a logic scheme which are suitable for implementation in the device, identifying an executable function and any needed parameters in the logic scheme, identifying the logic flow in the scheme, providing for at least two connected system resources to implement the logic scheme, selecting an op code, and providing a way to implement the various components needed to call and execute the function according to the logic scheme. A useful op code may invoke a system resource, implement the logic scheme, pass a parameter to the function, or invoke the function. The configurable hardware system can function as a CPU, using logic resources including a next address RAM, one or more registers, a function execution controller, and one or more busses for passing signals and data between the components and functions.

Abstract: A local bus interface for providing high-speed data transfer between the local bus of a personal computer and one or more data storage devices. The local bus interface bypasses the standard expansion bus (ISA, EISA, Micro Channel) on the personal computer, is directly connected to the local bus, and is transparent to the system software.

Abstract: The present invention provides for the updating of both the instructions in a branch prediction cache and instructions recently provided to an instruction pipeline from the cache when an instruction being executed attempts to change such instructions ("Store-Into-Instruction-Stream"). The branch prediction cache (BPC) includes a tag identifying the address of instructions causing a branch, a record of the target address which was branched to on the last occurrence of each branch instruction, and a copy of the first several instructions beginning at this target address. A separate instruction cache is provided for normal execution of instructions, and all of the instructions written into the branch prediction cache from the system bus must also be stored in the instruction cache. The instruction cache monitors the system bus for attempts to write to the address of an instruction contained in the instruction cache.