Abstract: A data retrieval and acquisition system having a wireless handheld interface for data entry by the user. The system includes a communication server for communicating, such as through IR signals, with the handheld interfaces. The communications server communicates with multiple command servers and with a master server and/or other communication servers through a communications bus. The handheld interface includes touch screen which is operated through an event driven architecture. The user is allowed to enter data through virtual rolling keys, a scroll bar, virtual key pad, bar code reader, and the like. The system minimized the transmission time by minimizing the necessary information transmitted and by synchronizing the operation of the handheld interfaces with the corresponding communications server. The communications server transmits information to the handheld through a first unique protocal and to the command server through a second unique protocal.

Abstract: A method and apparatus for modeling the exposure of spacecraft-mounted solar power panels to the sun over a given time interval, such as an orbit period, and a method and apparatus for modeling the drag of spacecraft over a given time interval, such as an orbit period. The result of the exposure modeling can be used to determine varying availability of electrical power for operations to be performed by the spacecraft and on-board apparatus. The results of the drag over time are used to predict orbit decay and fuel requirements for orbit maintenance and station-keeping. The invention uses a graphically based satellite systems analysis program to approximate exposure and drag data through visual projection of the relevant spacecraft elements on a computer display screen.

Abstract: A communication network having a plurality of nodes and a controller, a plurality of intermediate nodes in communication on a one-to-one basis with the plurality of first target nodes to be programmed. A first file containing a first executable program is transferred in parallel to each of the intermediate nodes. Intermediate nodes then, in parallel, program a respective first target node. The intermediate nodes may begin programming a respective first target node upon receipt of a sufficient portion of the first file to initiate programming or may begin upon receiving the complete first file. The intermediate nodes may also have connected thereto a respective second target node and may program the second plurality of target nodes simultaneously and in parallel using either the first file already transferred or a second file containing a second executorial program transferred in parallel.

Abstract: A method for simulating an impurity distribution in a multilayer structure includes analytically simulating an impurity distribution for each layer to obtain a first impurity distribution profile for each layer by using impurity distribution moments defined for the material of each layer, analytically simulating a point defect distribution for a crystal layer to obtain a point defect distribution profile by using the first impurity distribution profile and point defect distribution moments defined for the material of crystal layer, simulating a thermal diffusion to obtain a final impurity distribution profile for each layer by using the first impurity distribution profile and point defect distribution profile. The point defect distribution moments are obtained previously for the material of the crystal layer by Monte Carlo method under typical conditions to obviate using the Monte Carlo method for each simulation under a specified condition.

Abstract: A technique for automating the assembly of networked, language independent objects into a network application for use in a distributed object computing system uses program templates and a symbol table. A schematic representation of the network application is formed within a visual application builder. The schematic representation defines connections among representations of previously defined distributed objects. These connections are formed among parts, plugs and sockets that are associated with representations of distributed objects termed components. The schematic representation of the network application is loaded into a symbol table and portions of the schematic representation are stored as a number of entries in the symbol table. These entries include identifier-value pairs; that is, identifiers are mapped to values. The program source files to be generated are determined and the program templates for use in generating the program source file are also determined.

Abstract: An interface apparatus for SDH/SONET interconnection includes a transmission interface section provided at a position where an apparatus of the SDH system and an apparatus of the SONET system face each other and adapted to transmit a signal toward an apparatus of a different system. The interface apparatus for SDH/SONET interconnection further includes a mode setting unit for setting a mode suitable for an apparatus of a counterpart system, a frame synchronization information inserting unit provided in the transmission interface section and adapted to insert frame synchronization information corresponding to the mode set by the mode setting unit, and an overhead information inserting unit provided in the transmission interface section and adapted to insert overhead information corresponding to the mode set by the mode setting unit. This structure makes is possible to easily interconnect apparatuses of different systems (apparatuses of the SDH system and the SONET system) so as to operate them.

Abstract: A system for digital simulation of an electric circuit is disclosed. The system is event-driven, and functions on a gate inversion principle, to simulate an electric circuit. According to the gate inversion principle, any gates or gate arrangements in the circuit for which the input does not change are not simulated. A machine readable circuit description is generated which includes the gates and the gate arrangements for the circuit. Translation means creates data structures suitable for simulation of the circuit. Simulation means creates a program which schedules the simulation of only those gates or gate arrangements whose outputs change value during the simulation. According to the preferred embodiment, the simulation means uses only inversions of signals from individual gates or gate arrangements to perform the simulation of the circuit. Furthermore, the translation means includes means for removing any NOT gates from the circuit, and means for collapsing all homogeneous connections in the circuit.

Abstract: A microprocessor die contains several processor cores and a shared cache. Trigger conditions for one or more of the processor cores are programmed into debug registers. When a trigger is detected, a trace record is generated and loaded into a debug queue on the microprocessor die. Several trace records from different processor cores can be rapidly generated and loaded into the debug queue. The external interface cannot transfer these trace records to an external in-circuit emulator (ICE) at the rate generated. The debug queue transfers trace records to the external ICE using a dedicated bus to the ICE so that bandwidth is not taken from the memory bus. The memory bus is not slowed for debugging, providing a more realistic debugging session. The debug buffer is also used as a video FIFO for buffering pixels for display on a monitor. The dedicated bus is connected to an external DAC rather than to the external ICE when debugging is not being performed.

Abstract: A computer virus trapping device is described that detects and eliminates computer viruses before they can enter a computer system and wreck havoc on its files, peripherals, etc. The trapping device creates a virtual world that simulates the host computer system intended by the virus to infect. The environment is made as friendly as possible to fool a computer virus into thinking it is present on the host, its intended target system. Within this virtual world, the virus is encouraged to perform its intended activity. The invention is able to detect any disruptive behavior occurring within this simulated host computer system. It is further able to remove the virus from the data stream before it is delivered to the host and and/or take any action previously instructed by a user.

Abstract: The present invention has the following arrangement. That is, an instruction stream for performing an instruction simulation is analyzed before the instruction simulation is started to predict a timing at which interruption occurs, an interrupt generating unit generates a predictive interrupt signal one instruction cycle before interruption occurs on the basis of the prediction result, and, when an instruction which is executed immediately after the predictive interrupt signal is generated has a flag-less instruction identifier, an execution process of the instruction which is executed immediately after the predictive interrupt signal is generated is performed according to not a flag-less instruction code but a flag instruction code.

Abstract: An emulator apparatus includes an access information memory in which, when an emulation program makes a write access to a memory address of a microcomputer, and information showing the presence of the write access is related to the write-accessed address and is stored. A break circuit to break execution of the emulation program when the emulation program makes a read access to the memory address of the microcomputer is provided, and the access information memory does not contain information showing the presence of the write access to the read-accessed address.

Abstract: A system for managing an assemblage of entities. The entities interface within the assemblage for control of primary information handling functions and further interface with the system to permit the carrying out of management functions. The system includes management modules adapted to carry out management functions by independently interpreting and executing commands, a kernel including a table of dispatch pointers for directing the commands to the respective modules in which they are to be interpreted and executed, and an enroller for enrolling new modules into the system by adding further pointers to the table.

Abstract: A method for re-configuring a pre-compiled discrete-event digital simulation program. The method comprises the steps of creating a template having a series of generic tasks and incorporating the template onto a computer to create a generic computer simulation. Next information associated with the steps of a process are input on the computer. The information includes the time duration of each step and the resources expended in accomplishing each step. Finally, the step information is applied to the generic computer simulation to create the discrete event simulation model of the process.

Abstract: A system and method for eliminating the critical path of a processor-based system by sending a signal to transition memory and/or I/O control units to a READ/WRITE state prior to the end of the complete instruction decode. If the decoding phase of the opcode of the instruction reveals that a read-write step is to be carried out wherein memory or an I/O device must be accessed, the processor immediately sends a read-write request to the memory control unit and the I/O control unit prior to decoding the balance of the instruction. Once the balance of the instruction has been decoded and the access location is determined to be in either memory or an I/O device, a cancellation process takes place. In this cancellation process, if the access location is in memory, the I/O unit transitions from the read-write state to an idle state. If, however, the access destination is determined to be an I/O device, the memory control unit transitions from the read-write state to the idle state.

Abstract: A tool for providing user-configurable earcons, i.e. auditory cues, includes an earcon event engine responsive to command messages issued by tasks executing on a computer system. The command messages include an index to an earcon data file, which, in turn includes a reference to an audio file and audio parameter data for manipulating the acoustic parameters of the audio wave. A file interpreter provides the audio parameters to an audio processor for generation of the earcon. In one embodiment, the invention can be utilized with MIDI compatible instruments or sound cards.

Abstract: A method and apparatus for outputting a current state of a real-time circuit emulator. When the emulator is set to a predetermined state, it checkpoints the contents of certain memory and registers at the time it enters the predetermined state. The output of the emulator can be used as input to the emulator or as input to another system, such as a simulator, which does not operate in real-time. If the simulator also generates an output having same format, the output of the simulator can also be input to the real-time emulator.

Abstract: A new class of purpose computers called Programmable Reduced Instruction Set Computers (PRISC) use RISC techniques a basis for operation. In addition to the conventional RISC instructions, PRISC computers provide hardware programmable resources which can be configured optimally for a given user application. A given user application is compiled using a PRISC compiler which recognizes and evaluates complex instructions into a Boolean expression which is assigned an identifier and stored in conventional memory. The recognition of instructions which may be programmed in hardware is achieved through a combination of bit width analysis and instruction optimization. During execution of the user application on the PRISC computer, the stored expressions are loaded as needed into a programmable functional unit. Once loaded, the expressions are executed during a single instruction cycle.

Abstract: Improved parallelism in the generated schedules of basic blocks of a program being compiled is advantageously achieved by providing an improved scheduler to the code generator of a compiler targeting a multi-issue architecture computer. The improved scheduler implements the prior-art list scheduling technique with a number of improvements including differentiation of instructions into squeezed and non-squeezed instructions, employing priority functions that factor in the squeezed and non-squeezed instruction distinction for selecting a candidate instruction, tracking only the resources utilized by the non-squeezed instructions, and tracking the scheduling of the squeezed and non-squeezed instructions separately. When software pipelining is additionally employed to further increase parallelism in program loops, the improved scheduler factors only the non-squeezed instructions in the initial minimum schedule (initiation internal) size calculation.

Abstract: A physical design automation system for producing a highest fitness cell placement for an integrated circuit chip includes a decomposition/recomposition processor for decomposing a cell placement optimization process into a plurality of tasks and recomposing the highest fitness cell placement from results of performing the tasks. A plurality of worker processors independently perform the tasks and produce results. A host processor distributively assigns the tasks to the worker processors in response to work requests received therefrom. Each worker processor sends a work request to the host processor after completing a task. The host processor maintains a list of unassigned tasks, assigned tasks and completed tasks, and revises the list to redesignate assigned tasks as unassigned tasks upon determining that the list includes no unassigned tasks and at least one assigned task, thus making the system immune to the failure of one or more processors.

Abstract: A method and apparatus for emulating a change-of-state (COS) report network fully tests a monitor and/or control system (MCS). The communication and behavior of a COS report network are emulated for selected report network configurations, events, and/or COS indications. A communication module communicates with the MCS through emulator links using a communications protocol substantially identical to a communications protocol used in the emulated report network. A configuration database stores configuration data representing the current status of the report network of state monitoring devices. In response to MCS polling, an emulator message generator generates intelligent responses based on the configuration data which emulate communications from a report network of state monitoring devices to the MCS in response to such MCS polling. Simulated multi-tasking and dynamic user-interface control options are included.