Abstract: An otherwise conventional CardBus adapter is provided with an additional status register, a small number of additional pins, and associated external buffering circuitry. Furthermore, a number of the CardBus adapter's existing pins are either eliminated, redefined or used for multiple purposes. As a result, the CardBus adapter in conjunction with the associated external buffering circuitry is able to interface to multiple CardBus/16-bit PC Cards at the same time.

Abstract: A data processor comprises storage (e.g., registers) for each of first, second and third values, a processor condition register for processor condition codes, and logic for decoding instructions including a specific instruction defining an operation between the first value and either the second value or the third value, the selection of the second or the third value being made by the processor in dependence on the state of said processor condition code. The invention is of particular, but not exclusive, application for the plotting of lines in a display system. In an example of a display system incorporating such a data processor, a pixel can be plotted on each processor instruction cycle.

Abstract: A method and system are disclosed for tracking the allocation of resources within a processor having multiple execution units which support speculative execution of instructions. The processor includes a resource counter including a first counter and a second counter and a number of resources, wherein one or more of the resources are allocated to each of a number of instructions dispatched for execution to the execution units. In response to dispatching an instruction among the plurality of instructions to one of the execution units for execution, the first counter is incremented once for each of the resources allocated to the instruction, and if the instruction is a first instruction within a speculative execution path, the second counter is loaded with a value of the first counter prior to incrementing the first counter.

Abstract: Paths from a block that includes the node that is the object of analysis to another block are searched for by a path search section for all blocks in a circuit; and a depth judgment section finds the depth of each block from that path search information. An effective block judgment section compares the depth of each block to a specified depth that is stored in a specified depth storage section, and judges which blocks are effective blocks. Thus, blocks that include nodes that exert influence on the simulation accuracy at the node that is the object of analysis are extracted from the circuit that is the object of simulation as effective blocks. Then, in the circuit simulation, events are generated only for the effective blocks, and a transient analysis simulation is executed by the event-driven method. This permits the processing speed of the simulation to be increased while maintaining accuracy.

Abstract: Described is a circuit modifier, network, and method for use with an event-driven digital logic simulator for enforcing consistent evaluation of input pin changes at state elements. The invention automatically interposes a fictitious 0-delay defer agent or processor, at the input pin to state elements such as D Flip-Flops. The interposition of the defer agent is handled by the simulator as follows. Defer agents schedule events related to input state changes on a special time or task queue which is not processed until after all other events have been executed for the current time, including any extra iterations caused by 0-delay scheduling activity. Defer agents or processors are placed in a simulation network just prior to one or more of the input pins of state elements, the effect of which is to delay events that normally would propagate to the input pin of a state element until all other normal simulation events are processed.

Abstract: The present invention teaches a variety of methods, data structures and apparatus for use in representing and traversing hierarchical netlists. According to a first embodiment of the present invention, a hierarchical netlist which represents an electronic device is stored in a computer readable medium and includes a module data structure and a hierarchical data structure. The module data structure includes a first module and a list identifying each instance of the first module present in the hierarchical netlist. The hierarchical point data structure represents a first hierarchical element in the hierarchical netlist and is arranged to identify a selected device element represented in the first module. Additionally, the hierarchical point data structure is capable of identifying a plurality of unique occurrences of separate but identical device elements that are represented by the first hierarchical element.

Abstract: A computer modeling and visualization system employs both 3D visual modeling and force feedback through a haptic device consistent with the visual display of the computer model. Force, or haptic, interaction is employed for exploring computer models. Point contact force equations were created for quickly computing forces directly from a model data which are provided to the haptic device, causing it to apply that force to an operator. The force equations employed are consistent with isosurface and volume rendering, providing a strong correspondence between visual and haptic rendering. The method not only offers the ability to see and feel the volumetric model but allows interactive modification and display of the model.

Abstract: A cell library (21) is optimized for specific operating characteristics. A stimulus file (23) is divided into a number of simulation run files. The simulation run files (27) are distributed to more than one computer work station so that the simulation of the cell occurs in parallel. The netlist (24) of each cell is parameterized to allow the cell to be changed and resimulated to better meet the specific operating characteristics. A cost function (32) is provided which uses the results of a transistor level simulation to calculate the quality of the cell design relative to the specific operating characteristics. Simulated annealing (34) is used to generate new simulation parameter values from a cost generated from the cost function (32). The cell is resimulated a number of times to optimize for the specific operating characteristics and the best design is retained for a new cell library (39). The process is repeated for each cell of the cell library (21).

Abstract: A system and method for storing object information on a persistent medium. A DefaultEncoderDecoder is supplied that encodes object persistent attribute data into a string of attribute names, types and data values. The encoding and decoding is managed by one or more get and one or more set methods. The get methods control storing of the data while set methods control restoring of persistent data. Encoded strings of attribute data are upwardly compatible through replacement or overriding of the set methods.

Abstract: An apparatus for providing register compatibility between integrated circuits having different register and interrupt configurations is designed to operate with software. Software may attempt non-native register accesses; the integrated circuit of the present invention will emulate a non-native register set. In the preferred embodiment only one physical register set is included on the integrated circuit and a compatibility engine is used when a non-native register access is attempted. The compatibility engine is coupled between a bus interface unit and the physical register set and allows a user or system designer to address a register set of another integrated circuit having a different configuration than the physical register set. The compatibility engine converts the address and maps the data bits of the emulated register into registers within the physical register set. Alternatively, two sets of registers can be physically included on the integrated circuit.

Abstract: An image synthesis and display apparatus. The apparatus includes a display device, an image pickup device, an extraction unit and a synthesis unit. The display device displays a simulation image to a user, and provides a field of view of the simulation image to the user. The image pickup device detects an image of a range of an actual space corresponding to the field of view provided to the user by the display device. The extraction unit extracts an image of an object from the image detected by the image pickup device. The synthesis unit inserts the image extracted by the extraction unit into a simulation of a virtual space, to produce the simulation image displayed by the display device. The image pickup device is aligned with the display device, and the image pickup device and the display device move with the user while maintaining the alignment between the image pickup device and the display device.

Abstract: In a computer system where a plurality of bus masters are connected to a bus, a bus arbiter connected to the bus, comprises an arbitration circuit that arbitrates between the bus access request signals from the plurality of bus masters and outputs a bus access grant signal to a single bus master of the plurality of bus masters, unit for holding a value indicating the duration during which the switching of the bus access grant signal is to be inhibited, counting unit capable of counting on the basis of the value held in the holding unit, unit for causing the counting unit to start counting at the time when the arbitration circuit has given a bus access grant signal to a bus master, unit for inhibiting the arbitration circuit from switching the bus access grant signal in the period until the counting has been completed, as long as the bus access request signal from the bus master to which the bus access grant signal has been given remains active, and unit for permitting the arbitration circuit to switch the acc

Abstract: A method and system for the enhanced efficiency of data transfers from memory to multiple processors in a data processing system. Each of the multiple processors has an associated buffer for storing data transferred via a common bus which couples the processors and memory together. Each of the multiple processors continually monitors the common bus and is capable of asserting a selected control signal in response to an attempted activity of another one of the multiple processors which would violate data coherency within the data processing system during a particular period of time following the attempted activity. Data is transferred from memory to a buffer associated with one of the multiple processors and stored in the buffer in response to a request from the processor associated with the buffer prior to expiration of the particular period of time and prior to a determination of whether or not this transfer will result in a possible data coherency problem.

Abstract: A peripheral interface system and apparatus including a pair of integrated circuits, referred to as a system adapter and a socket controller, use a communication protocol, referred to as a windowed-interchip-communication protocol, to interface peripherals, such as PCMCIA cards or infrared devices, and other subsystems having different formats with a CPU system bus. The system adapter communicates to a hard disk drive subsystem using the ATA communication standards to interface an ATA hard disk drive with the CPU system bus. Communication between the system adapter and the socket controller, which communicates with PCMCIA peripheral cards and IR peripherals, is accomplished using the windowed-interchip-communication protocol which may share hardware resources with other communication protocols. Communication between the system adapter and the hard disk drive and between the system adapter and the socket controller may be provided on the same chain of a standard 40 signal ribbon cable.

Abstract: A low cost electrical network analyzer that provides waveform predictions in the time domain of a device for any electrical signal stimuli and with any load. In a preferred embodiment, input, output and stimulating source waveform recorders are used to record tables of time domain data (voltage waveforms) derived by stimulating the device under test with and without an output load coupled thereto. The tables of time domain data are representative of input and output signatures of the device. The tables are stored in a processor and are processed by way of a computer-implemented time domain network analyzer to produce sets of complex parameters as a function of time that are representative of the device. The parameters thus comprise a model of the analyzed device.

Abstract: A system and method is provided for that allows the introduction of small sections of idealized conductive elements to be placed along a transmission line. The output is a partitioned transmission line whose segments between the idealized conductive elements are analyzed via circuit simulators as a distributed parasitic network, as opposed to the widely used lumped parasitic elements approach for the entire line. The distributed parasitic network system and method provides circuit designers with a parasitic extraction tool which allows the designer to define a transmission line segment for analysis, and create sub-networks of parasitic elements across the transmission line. These elements can then be passed to existing vendor circuit simulators for parasitic analysis, the result of which are more accurate than that derived using existing extraction tools whose output is limited to only a lumped parasitic parameter along the line.

Abstract: A PCI-bus is added to a VESA local bus (VL-bus) computer system using a VL-bus/PCI-bus bridge. The VL-bus/PCI-bus bridge claims a VL-bus cycle by asserting LDEV# to the VL-bus/system-bus bridge. If no other VL-bus device claims the cycle as well, then the VL-bus/PCI-bus bridge translates the cycle onto the PCI-bus and awaits a response from a PCI device. If no PCI device claims a cycle by the PCI-bus device claiming deadline, then the VL-bus/PCI-bus bridge asserts BOFF# to the host and suppresses its assertion of LDEV# when the host repeats the cycle on the VL-bus. The VL-bus/system-bus bridge therefore can translate the repetition of the cycle onto the system bus. When asserting BOFF# to the host, the VL-bus/PCI-bus bridge also asserts the VL-bus device ready signal LRDY# after assertion of BOFF# and releases LRDY# before releasing BOFF#.

Abstract: In a multitasking data processing apparatus including means for executing processes and including a display adapter for executing functions supporting a display, the display adapter including a first port means for receiving, from the means for executing processes, requests to execute selected functions having a first execution priority, a second port means for concurrently receiving, from the means for executing processes, requests to execute selected functions having a second execution priority lower than the first execution priority, and means, coupled to the first and second port means, for executing selected functions according to the execution priority.

Abstract: A method of preparing a specification of a system for simulation on a computer system. The specification includes a hardware design language specification of the system. Analyze the specification to identify a set of processes, where each process includes a plurality of statements. Determine an evaluation order of the set of processes. Generate a combined process including a portion of the plurality of statements. The portion of the plurality of statements are included in the combined process so as to be evaluated according to the evaluation order.

Abstract: A method for generating a computer model for use in system component design as well as overall system evaluation is disclosed. The method includes the steps of generating an equation model of the system component, modifying the equation model by integrating according to the trapezoidal rule, wherein an integrated model is formed having a plurality of parameter values. Certain of such parameter values define historical parameter values accounting for historical parameter information. the parameter values are arranged in matrix form and reordered. The reorder matrix equation is reduced by eliminating certain of the parameter values, thereby forming a reduced model. When the reduced model is incorporated is a system model it is necessary to modify the system model to account to the component model current parameter information. Such information is used by the component model to update the historical information.