Abstract: In accordance with the present invention, a circuit 50 for providing a branch decision signal based on the results of an arithmetic or logic operation is described. The circuit comprises at least two candidate branch decision circuits 52,54,56,58, each for computing a candidate branch decision signal, each assuming a unique candidate condition code for at least one of the alu status signals. The circuit further comprises a first selection circuit 62,64,66 for selecting from the candidate branch decision signals a proper branch decision signal based on the alu status signal at such time as the status signal becomes valid. Other devices, systems and methods are also disclosed.

Abstract: A bit data processor includes bit data input device, an indicator for indicating a shift distance of the bit data inputted by the input device and modifying the indication data in accordance with an output position of the bit data, and memory means for receiving, as an address, the bit data supplied by the input means and the indication data supplied from the indication means to output a shifted bit data.

Abstract: An interface circuit for an IDE-type CD-ROM drive connected to a personal computer using a standard IDE interface according to a hard disk drive interface standard includes a drive selecting circuit for generating a buffer gate signal a control circuit for generating a command signal, a drive read signal, a drive write signal and a drive reset signal responsive to an IDE port address, an input/output read signal, an input/output write signal and a reset signal, for providing the received signal to the IDE interface by receiving handshake signals, a data buffer for transmitting the data in a specified direction determined according to the drive read signal, and a master-slave communication circuit for generating communication signals in response to a reset signal from the IDE interface.

Abstract: A bit data processor includes bit data input device, an indicator for indicating a shift distance of the bit data inputted by the input device and modifying the indication data in accordance with an output position of the bit data, and a memory for receiving, as an address, the bit data supplied by the input device and the indication data supplied from the indicator to output a shifted bit data.

Abstract: An information processing apparatus having two or more functions, in which one of the functions is automatically selected according to the state of an external memory device, or according to the actuated one of plural input devices, without an instruction by the operator.

Abstract: An information processing apparatus includes a change point detection unit for obtaining dot change point positions and the number of change points in units of scanning lines by scanning a dot pattern in a predetermined direction, a discrimination unit for discriminating start and end positions of a dot set by scanning the dot pattern in the predetermined direction so as to detect appearance of a noncontinuous dot pattern in a direction substantially perpendicular to a direction of the scanning line, and a generation unit for generating information representing, as a relative value with respect to the immediately preceding scanning line, the change point positions and the number of change points detected by the change point detection unit and the start and end positions of the dot set discriminated by the discrimination unit in accordance with an external instruction.

Abstract: A high-performance CPU of the RISC (reduced instruction set) type employs a standardized, fixed instruction size, and permits only simplified memory access data width and addressing modes. The instruction set is limited to register-to-register operations and register load/store operations. Byte manipulation instructions, included to permit use of previously-established data structures, include the facility for doing in-register byte extract, insert and masking, along with non-aligned load and store instructions. The provision of load/locked and store/conditional instructions permits the implementation of atomic byte writes. By providing a conditional move instruction, many short branches can be eliminated altogether. A conditional move instruction tests a register and moves a second register to a third if the condition is met; this function can be substituted for short branches and thus maintain the sequentiality of the instruction stream.

Abstract: An apparatus for controlling the transfer of data comprises registers for setting an address of a memory and data to be stored in the memory at the address, and a control unit for controlling the registers to set the address and data. In a case where an immediate data transfer command is produced, a physical address is defined by including the immediate data transfer command partly therein. The physical address thus defined is automatically set in the register for setting an address of a memory without receiving an address setting command so that the data stored in the register for setting data are written into the memory at the physical address.

Abstract: Methods for operating a modeling system and/or a communications network, using a computer assisted process, are described, which transform a first set of signals, including (a) signals representing a given linear network defined in terms of a set of node identification signals, (b) a set of weighted/directed edge signals each of which identify the weight, direction and the pair of nodes in the network interconnected via a given edge, and (c) signals representing arbitrarily specified start and target nodes in the network, into a second set of signals indicating the shortest path in the network between the start and target nodes. The processes contemplated by the invention perform the aforementioned transformation by incrementally creating an array of node identification signals directly from the first set of signals. No starting matrix (or sparse matrix), as required by prior art processes, needs to be created or stored.

Abstract: A system and method for recording accounting times by an Agent in a network and retrieving the accounting times by the network Manager. Three types of data objects in each of the Agent's stored records are provided. Record Number is the sequence number of the record in the file. Recording time is an indication of the time the record was stored in the file since a certain point in time, such as after the Agent's clock began running. Record Type is the particular type of record stored. The Record Type can either be DATA representing normal accounting data or TIME representing time data used for correlating the Manager's and the Agent's time-keeping. Upon receipt of an accounting data record of type DATA, the manager uses the record's Recording time to help determine the point of time accorded to that event. The Manager then uses the previous record of type TIME to adjust the Recording time of the received accounting data record relative to the Manager's precise calendar time.

Abstract: A digital signal processor evaluation chip has a sequencer for fetching and decoding instructions, and a processor core for executing the instructions. When the sequencer attempts to fetch an instruction from a preset break address, a register transfer instruction is supplied in place of the program instruction at that address, then clock input to the sequencer is halted. After the processor core has executed the register transfer instruction, clock input to the processor means is also halted, leaving the data transferred by the register transfer instruction available to be read.

Abstract: A method and apparatus for automatically generating device names in a computer system, wherein device names are generated to reflect the physical realities of system configuration. An existing device driver interface is employed, wherein a parent device driver's bus.sub.-- ctl function, along with a child device driver's probe and attach routines, are used to generate device names.

Abstract: A method and apparatus for defining a context environment of an editor applet which is processing data to be stored in a container applet. In the invention, a first applet is executed and the context environment indicative of the first applet is stored. A second applet is executed and examines the stored context environment indicative of the first applet. In accordance with the result of the examination, the second applet modifies its operation.

Abstract: A microcomputer development support system for a microprocessor, includes an instruction substituting circuit tracing a memory access performed by the microprocessor and substituting a predetermined branch instruction for an instruction which is read out from a predetermined address of a user memory by the microprocessor, and a background monitor configured to give the microprocessor a memory space which is separated from the user memory but is peculiar to the microcomputer development support system. After the predetermined branch instruction has been substituted and after a break acknowledge signal informing an execution of the predetermined branch instruction has been activated, the microcomputer development support system executes a program stored in the background monitor. At the same time, the microcomputer puts the cache memory into the "cache off" condition when it starts to execute the program of the background monitor.

Abstract: A method and apparatus is provided to simulate a system that is modelled by object frames which describe information on the events to be processed by the system, and a root frame that contains information on the conditions and times of the simulation. The first step is to search for an (accidental simultaneous state-events) object, which causes an event at the time prescribed by the root frame, by sequentially referring to the scheduled occurrence times of the events so as to execute simulation of the object, the second step is to list the events (intentional simultaneous state-events), which simultaneously occur with the searched-for object, referring to a simultaneous state-events rule, so as to execute simulation of an object causing the event, and the first and the second steps are repeatedly executed until completion of the simulation time, by updating the time of the root frame when processing of both steps is complete for all objects searched for in the first step.

Abstract: A distributed network monitor system distributes the network monitoring function among each of the nodes of a multiple network system, such that monitor software resident in each node is responsible for providing status information about that node and its communications links. At predetermined monitoring intervals, a circulating status table (CST) (FIG. 4) is circulated to all of the on-line nodes, with each node updating the CST with its link and status information. The monitor software (FIG. 1) includes a servicer task (22), a node monitor task (24), and a packet manager task (26), with intertask data transfers being implemented through a monitor region (28) in memory. In addition to link and node status information, the CST includes information about links that are in an intermittent condition (i.e., links with significantly degraded statistical performance).

Abstract: When a copy process is successively performed twice or more and an input buffer in a program storing portion holds a data packet, a new data packet is generated based on a data packet input to an information fetching portion, and the new data packet is output. At the same time, 1 is added to the destination information of the data packet input to the information fetching portion and a through packet flag of that data packet is set to "ON", and the data packet is output. The data packet with the through packet flag set to "ON" passes through a data pair detecting portion and an operation processing portion without being subjected to any processing, thereby returning to a program storing portion. A copy process is performed based on the returned data packet.

Abstract: An information processing system includes an instruction decoder part for decoding an external instruction signal and for outputting a control signal for executing an instruction based on a decoded result, and an operation part for carrying out an operation based on the control signal and for outputting an operation result. The operation part includes an operation unit which carries out an arithmetic logic operation and outputs the operation result, a flag register for holding states related to the operation result based on the control signal, and a buffer for successively holding predetermined states related to the operation result. The operation unit carries out the arithmetic logic operation by selectively reading the states held in the flag register and the buffer.

Abstract: A microcomputer comprising an internal decoder for addressing instruction codes in an instruction prefetch buffer, a words field provided preferably in a micro ROM for storing number of words which indicate lengths of various instructions, and position calculating means provided in the bus interface unit for inputting the number of words to indicate an address of instruction code in the instruction prefetch buffer, so that the instruction code is read out concurrently with the execution of the micro instruction.

Abstract: The present invention employs a generative approach for configuring systems such that a system may be configured based on component or resource requests, or input in the form of need. The present invention provides a constraint-based configuration system using a structural model hierarchy. The structural aspects of the model provide the ability to define a model element as being contained in, or by, another model element. In addition, the structural model provides the ability to identify logical datatype and physical interconnections between elements and establish connections between elements. To configure a system, the present invention accepts input in the form of requests (e.g., component or resource) or needs, such as an expression of a need for a desktop computer system to be used in a CAD (i.e., computer-aided design) environment.