Abstract: A circuit by which an SWI instruction held in a memory circuit is switchedly input in response to a signal supplied externally is provided in a processor, whereby the substitution of a program word can be realized using such an internal circuit, so that a high-speed and reliable break in program execution can be effected. Moreover, an interrupt function separate from normal interrupts is established by setting a specified operation mode, whereby, when a data processor is used as an emulator, the break of a user program including the ordinary interrupt processes can be easily effected by utilizing the special interrupt function. Also, by additionally providing the function of delivering out a signal indicative of the break status, an external circuit can be simplified.

Abstract: An architecture and method for operating a work station. The work station includes a CPU, a bus interface unit and a control line. The CPU is selected from a group of CPUs differing in certain operational parameters. The bus interface circuit is connected between an external bus and the CPU. The control line is connected to the interface circuit and provides a signal indicating the type of CPU connected to the circuit.

Abstract: Multi-media computer system diagnostic system for fault isolation in a multi-tasking hard, real-time task environment is described. Hard, real-time multi-tasking operations, particularly those unique to signal processing tasks may be monitored without creating a task processing overload and without delaying the results beyond hard, real-time task deadlines by insertion of a branch instruction in the task execution instructions being examined which cause execution of the task to branch to a diagnostic program. The diagnostic program executes a diagnostic instruction set and captures one or more digital samples characteristic of the operation of the hard, real-time task at the point in its program execution where the branch instruction was located.

Abstract: A medical imaging system for communicating image information between a plurality of different input imaging devices having different input protocols and a plurality of different output imaging devices having different output protocols takes advantage of a reusable software architecture having a plurality of functionally independent components. The individual components can be configured in a communication pipeline to communicate image information between an input imaging device and an output imaging device according to desired protocols. Each component can be interchanged with a differently configured component to facilitate communication of image information according to a different protocol, thereby reconfiguring the pipeline to achieve significant flexibility. Moreover, the software architecture is scalable to produce a plurality of communication pipelines, each of which can be configured according to desired protocols.

Abstract: A decoder for decoding multiple instructions in parallel, including a full decoder that can decode an instruction into multiple micro-operations, and a partial decoder that can decode a subset of the full instruction set.

Abstract: A timing and control circuit and method for a synchronous vector processor (SVP) device having a plurality of one-bit processor elements organized in a linear array. This circuit includes a master controller circuit, a vertical timing generator circuit, a constant generator circuit, a horizontal timing generator circuit and an instruction generator circuit.

Abstract: A data processing circuit multiplies, by 2a, input data supplied in a time-division multiplexed manner over a plurality of lines. The data processing circuit includes first, second, and third data selectors each having first, second, and third input terminals and a single output terminal. The first input terminal of the first selector is supplied with an input signal of "0". A first input line is connected in common to the second input terminal of the first data selector and the first input terminal of the second data selector. A second input line is connected in common to the third input terminal of the first data selector and the second input terminal of the second data selector. A third input line is connected in common to the third input terminal of the second data selector and the second input terminal of the third data selector. The first, second, and third input lines are supplied input data in a time-division multiplexed manner.

Abstract: Delay circuitry is used in a circuit to delay the transmission of groups of data until another circuit expects these groups of data. In one embodiment, emulating circuitry is used to emulate the timing of transmitter and receiver UART FIFOs. This emulating circuitry uses delays equal to the amount of time the UART FIFOs take to serially shift out data in the transmitter UART FIFO, and to serially shift in data in the receiver UART FIFO. This allows the modem chip to use a parallel-to-parallel FIFO buffer for the transmitter FIFO buffer and the receiver FIFO buffer.

Abstract: A method of compressing data used in integrated circuit (IC) layout verifications includes the steps of identifying each circuit component from each layer of the IC chip; sorting each circuit component in an established order; identifying predetermined parameters for each component; determining the difference in value of the parameters for each pair of components in successive order; and storing the difference values for each pair of components.

Abstract: A signal processing system includes a compression encoder 16 for compressing an input block of data samples including a plurality of sub-blocks, each sub-block including an array of data samples, into a block of compressed data. A sequencer 14' accesses the data samples of the input block to be passed to the compression encoder 16 with the sub-blocks being accessed in a predetermined first order and the data samples within each sub-block being accessed in a predetermined pseudo-random order such that successively accessed locations in the array of samples for a sub-block are scattered throughout that sub-block. The pseudo random accessing sequence enables occupancy of a buffer 73 for the compressed data block to be linearised. The sequencer can include a counter 62, the output of which addresses a look-up table 65 for generating the pseudo-random sequence in a repeatable manner.

Abstract: An apparatus for producing an operational manual of an integraged services digital network (ISDN) terminal and supplying the same to an operator of the ISDN terminal. The operational manual teaching how to operate a minimum procedure to obtain one of functions. Each of the functions includes the plurality of minimum procedures which can no longer be segmented. The ISDN terminal and the apparatus are coupled to the ISDN terminal via the ISDN. The operator of the ISDN terminal requires the operational manual by means of a predetermined called party subaddress or a dial-in which are defined by CCITT. Since the apparatus produces the operational manual by properly combining the minimum procedures, the operational manual can satisfy the various levels of skills of the operator.

Abstract: A PCMCIA card having independent functionality and alternatively arranged to operate in conjunction with a host computer, that includes a peripheral apparatus (109) having an integral CPU (125), a power source (129), and a power supply (127) for exhibiting an independent operating state; and an interface function (121) integral with and coupled to said peripheral apparatus (109), said interface function arranged and constructed to couple said peripheral apparatus to the host computer (101) over a PCMCIA compliant interface and initiate a dependent operating state at said peripheral apparatus (109).

Abstract: A peripheral card (109) having an adaptive PCMCIA compliant interface including either an adaptive card present or card configuration function that includes a peripheral apparatus (209) arranged and constructed to operate in conjunction with a host computer (101) over a PCMCIA compliant interface, and an interface logic (205), coupled to the peripheral apparatus (209) and to a PCMCIA peripheral port (201), for interfacing the peripheral apparatus to the PCMCIA peripheral port (201), the interface logic further adaptively providing a card present signal at the PCMCIA peripheral port (201) when the peripheral apparatus (209) and the interface logic (205) expects the PCMCIA peripheral port (201) to be activated by the host computer (101) or alternatively adaptively providing configuration information pertaining to the peripheral apparatus to the host computer.

Abstract: A processing method by a processor operating under a pipeline control mode, in which first instruction information data are fetched in a first operating cycle of a series of operating cycles and processing in accordance with the first instruction information data is executed in the following second operating cycle, at the same time that second instruction information data is fetched. When an interrupt demand is made in a given operating cycle, address data of Instruction information data fetched during the operating cycle and address data of instruction information data fetched during an operating cycle following the operating cycle are saved. Instruction information data specified by the two address data are fetched and executed on termination of an interrupt processing performed in response to the interrupt demand.

Abstract: A system for managing an assemblage of entities. The entities interface within the assemblage for control of primary information handling functions and further interface with the system to permit the carrying out of management functions. The system includes management modules adapted to carry out management functions by independently interpreting and executing commands, a kernel including a table of dispatch pointers for directing the commands to the respective modules in which they are to be interpreted and executed, and an enroller for enrolling new modules into the system by adding further pointers to the table.

Abstract: A method allows a designer to implement software for a wide variety of variant host architectures, without excessive usage of host memory, nor sacrificing the capabilities of high end versions of the variant architectures available. The method is based on providing an initialization module of the software to host memory. A portion of the initialization module determines the host architecture. Based on the determined host architecture, the unneeded portions of the initialization module are freed, and the needed portions are relocated into a contiguous memory space to minimize host memory usage. Any location dependent entries in the needed portions of the program are then updated based on the relocation. The initialization module includes a plurality of code blocks, each of which is optimized to a particular variant architecture. When the variant architecture of the host is identified, those code blocks which are optimized to the identified host are selected and the other code blocks are freed.

Abstract: A FIFO queue is utilized to provide control information to the appropriate time slot in a time multiplexed serial link between an interface chip and a CODEC. The FIFO queue allows rewriting or replacement of any control registers present in the queue without requiring that a new entry be placed in the queue. A particular control register which is placed in the queue then maintains its place as the queue is emptied, even though the control register may be written one or more times while the control register entry is in the queue waiting for transmission to the CODEC. The loss of the prior command information is not a problem as the data rate of the serial link is still sufficiently high so that any minor transitory change which may have been desired would be of minimal effect in any regard and would have been inaudible to the human.

Abstract: In a small size computer, and particularly a portable personal computer, a streaming mode tape recorder is coupled via a plug connector for data protection or backup. A plug connector via which the tape recorder is connected includes line connections for data signal lines and control signal lines as well as power supply lines. The plug connector, when the tape recorder is not plugged in is covered by a pivotable door arranged at a wall surface of the computer housing, the door also including means for securing the tape recorder in the plugged position.

Abstract: In a multitasking data processing apparatus including means for executing processes and including a display adapter for executing functions supporting a display, the display adapter including a first port means for receiving, from the means for executing processes, requests to execute selected functions having a first execution priority, a second port means for concurrently receiving, from the means for executing processes, requests to execute selected functions having a second execution priority lower than the first execution priority, and means, coupled to the first and second port means, for executing selected functions according to the execution priority.

Abstract: A system for extending a communications link between a host computer and peripheral device provides true emulation of the peripheral data storage device. The system includes a host extender for communicating directly with the host computer and a peripheral extender for communicating directly with the peripheral device. The host attached and peripheral extenders communicate across the extended communications link. The host extender initially transmits a channel program to the peripheral extender. The system uses the channel program to obtain format information of a particular track of the peripheral device. The host extender stores this format information and uses it to emulate the peripheral device to the host computer.