Patents Examined by B. P. Davis
  • Patent number: 4849704
    Abstract: A phase detecting circuit for use in phase-locked loops is provided with a pair of bistable circuits such as type D flip-flops. One of the circuits is clocked by a reference input signal and reset by the Q output of the other circuit. The other circuit is clocked by a second data signal and reset by the NOT Q output of the first circuit. The average value of the voltage appearing on the NOT Q output of the first circuit is proportional to the phase difference between the reference data signal and the second data signal.
    Type: Grant
    Filed: April 15, 1987
    Date of Patent: July 18, 1989
    Assignee: Westinghouse Electric Corp.
    Inventor: Roger D. Thornton
  • Patent number: 4804865
    Abstract: A circuit for providing a fast stabilization of the reference voltage level produced by a reference generation circuit includes a clamping circuit which clamps the refernece node at a voltage approximately equal to the voltage produced by the reference generation circuit when the reference voltage level is disabled. When the reference generation circuit is enabled, the reference node has to be pulled only slightly to reach the proper reference voltage, thereby increasing the speed of the device and the clamping circuit is turned off.
    Type: Grant
    Filed: March 19, 1987
    Date of Patent: February 14, 1989
    Assignee: Harris Corporation
    Inventor: Jack E. Clark, II
  • Patent number: 4794274
    Abstract: A circuit arrangement for switching a current through the emitter-collector path of a bipolar transistor whose base receives a substantially square-wave switching signal from a switching generator via a series-arranged two-terminal network having inductive reactance. This signal switches the transistor alternately to the conducting and the non-conducting state. In such a circuit arrangement, a very short fall time of the current in the emitter-collector path of the transistor is achieved in a simple and economical way in that the value of the inductive reactance decreases when a current flowing through the two-terminal network increases.
    Type: Grant
    Filed: April 1, 1985
    Date of Patent: December 27, 1988
    Assignee: U.S. Philips Corporation
    Inventor: Klaus B. Lohn
  • Patent number: 4793674
    Abstract: A fiber optic coupler (15) is constructed by inserting optical fibers (11, 12) into a glass tube (23). Glass frit is placed in the glass tube (23) to fill-in the space between the optical fibers (11, 12) and the glass tube (21). The tube (23) is heated at a center portion (21), which fuses the glass frit and thereby strengthens the fiber optic coupler (15) at its critical cross-section. The coupler has high efficiency and structural stability, both of which are advantageous when used with fiber optic gyroscopes.
    Type: Grant
    Filed: January 16, 1987
    Date of Patent: December 27, 1988
    Assignee: Allied-Signal Inc.
    Inventors: Beth A. Buzzio, Eugenia M. Viera, Christine M. Flaherty, Arlene C. Isea, Herbert T. Califano, Joseph P. Pierry
  • Patent number: 4791314
    Abstract: A line driver circuit capable of operating at high speeds. The output transistor, an emitter connected to an output terminal, has a special feedback capacitor connected to its base. The feedback capacitor helps pull the output terminal high to increase the switching speed of the line driver circuit. Special current injection and removal techniques are used to speed the switching times of the PNP current supply transistors. The line driver circuit also has special circuitry to limit the output current from exceeding certain limits and for keeping the line driver circuit from overheating.
    Type: Grant
    Filed: November 13, 1986
    Date of Patent: December 13, 1988
    Assignee: Fairchild Semiconductor Corporation
    Inventors: James R. Kuo, Timothy G. Moran
  • Patent number: 4789793
    Abstract: A CMOS output pair provides rapid switching speed while avoiding excessive noise levels developed across the power supply parasitic inductance. Both the P-channel and N-channel transistors of the output pair actually comprise a plurality of sub-transistors with their source to drain current paths connected in parallel. As a result of novel RC coupling of a switching signal from gate to gate of either of the plurality of sub-transistors, the sub-transistors are caused to turn on sequentially. Since none of the sub-transistors is capable of supporting the current that must be carried by the totality of sub-transistors making up either the P-channel or N-channel transistor, the increments of current as each sub-transistor turns on are small relative to the total.
    Type: Grant
    Filed: February 24, 1987
    Date of Patent: December 6, 1988
    Assignee: Texas Instruments Incorporated
    Inventors: George J. Ehni, Jy-Der Tai, Edison H. Chiu, Thomas A. Carroll
  • Patent number: 4786827
    Abstract: Described is an antisaturation circuit for an integrated PNP transistor characterized by a comparator circuit comprising two transistors and a current generator whose output current corresponds to a pre-established function, e.g., an exponential function, of the emitter current of said transistor. The changing of state of the comparator circuit, as determined by said pre-established function of said current generator, is determined by the drop of the V.sub.CE voltage of the transistor below a preset minimum value, with a portion of the conduction current of one of the two transistors of the comparator circuit utilized for increasing the forced .beta. of the transistor. This limits the degree of its saturation, as well as the leakage current toward the substrate.
    Type: Grant
    Filed: June 26, 1986
    Date of Patent: November 22, 1988
    Assignee: SGS Microelettronica S.p.A.
    Inventors: Roberto Gariboldi, Marco Morelli
  • Patent number: 4785250
    Abstract: A capacitor simulator circuit comprises a first node, a first capacitor coupled between a second node and a reference potential, a second capacitor coupled between a third node and a reference potential, a resistor coupled between the first and third nodes, a first electrical switch arranged when in an open state to electrically isolate from one another the first and second nodes and when in a closed state to electrically coupled together the first and second nodes, a second electrical switch arranged when in an open state to electrically isolate from one another the second and third nodes and when in a closed state to electrically couple together the second and third nodes.
    Type: Grant
    Filed: January 19, 1983
    Date of Patent: November 15, 1988
    Assignee: Plessey Overseas Ltd.
    Inventor: Rodney J. Lawton
  • Patent number: 4783633
    Abstract: An integrable circuit arrangement for deriving a coincidence pulse on coincidences of the falling edges of pulses of a digital data signal with the falling edges of pulses of sampling signals obtained by frequency division and gating and intended for use in a digital data processing system is disclosed which requires little area on an integrated-circuit chip. It contains an input gate consisting of a first NOR gate and a second NOR gate which are cross-coupled. The sampling signal is applied to the first input of the second NOR gate, and one of the system clock signals to the first input of the first NOR gate. The first input of a third NOR gate is connected via an inverter to the output of the first NOR gate, while the data signal is applied directly to the second input of the third NOR gate, and the delayed data signal is applied to the third input in inverted form.
    Type: Grant
    Filed: May 19, 1987
    Date of Patent: November 8, 1988
    Assignee: Deutsche ITT Industries GmbH
    Inventor: Brian Woods
  • Patent number: 4777386
    Abstract: A driver circuit for a bipolar Darlington power transistor includes a current clamping device which is provided between the base and emitter of said transistor and makes the base-emitter path of said transistor operate at a shallow saturated region; and a cut off device which is provided at the side of said emitter and cuts-off said transistor in response to a signal given from a driving power source.
    Type: Grant
    Filed: October 19, 1987
    Date of Patent: October 11, 1988
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventor: Gourab Majumdar
  • Patent number: 4777392
    Abstract: A voltage repeater circuit for loads with a resistive component with harmonic distortion compensation includes first, second and third MOSFET transistors, respectively N-channel, P-channel, and N-channel. The drain electrode of the first transistor whose gate electrode forms an input terminal of the repeater circuit is connected to the positive terminal of a voltage source via a constant current generator and is coupled to the gate electrode of the second transistor by a first circuit designed to establish a constant voltage between these electrodes, and to the gate electrode of the third transistor, by a second circuit designed to generate a constant voltage between these electrodes. The source electrode of the first transistor is connected to the drain electrode of the second transistor and to the drain electrode of the third transistor at a circuit node which forms an output terminal of the repeater circuit.
    Type: Grant
    Filed: July 29, 1987
    Date of Patent: October 11, 1988
    Assignee: SGS-Thomson Microelectronics SpA
    Inventors: Franco Maloberti, Guido Torelli
  • Patent number: 4776660
    Abstract: A light branching element or diplexer comprising a first bi-directional light connection and a second and third unidirectional light connection. The unit is formed by a block having a straight surface groove with an embedded glass fiber which fiber is interrupted by a partially transmissive mirror lying on a slanting plane relative to the axis of the fiber. The light sensitive location of a light receiving semiconductor element is secured to the block adjacent to the mirror and the plane of the mirror is selected so that its normal extends out of the block at an angle of incidence smaller than 45.degree. to the axis of the fiber to reduce reflections from the semiconductor member back to the mirror and into the fiber.
    Type: Grant
    Filed: January 27, 1987
    Date of Patent: October 11, 1988
    Assignee: Siemens Aktiengesellschaft
    Inventors: Hans F. Mahlein, Herbert Michel, Achim Reichelt, Gerhard Winzer
  • Patent number: 4777387
    Abstract: A power MOSFET is controlled by illuminating a single photovoltaic generator which produces an output current which charges the gate capacitanace of the power MOSFET to turn on the device. A sensing impedance which may be a diode, MOSFET or other component is connected between the photovoltaic generator and the gate of the power MOSFET. The sensing impedance in the disclosed embodiment is a diode. The sensing impedance forces the power MOSFET gate voltage instantaneously to follow the photovoltaic generator output voltage. The diode is connected in series with the charging circuit and a switching transistor is connected in parallel with the gate capacitance of the MOSFET.
    Type: Grant
    Filed: February 21, 1984
    Date of Patent: October 11, 1988
    Assignee: International Rectifier Corporation
    Inventor: Howard W. Collins
  • Patent number: 4775803
    Abstract: The invention relates to technology to minimize power for suppressing ON base current to a transistor. In a base drive circuit of transistor, current is supplied to base of first and second transistors connected in series to DC power source, and the transistors are rendered on or off.
    Type: Grant
    Filed: April 13, 1987
    Date of Patent: October 4, 1988
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventor: Haruyoshi Mori
  • Patent number: 4774419
    Abstract: A transformer includes a secondary winding coupled to a load which may be the source and gate of a FET. The primary winding of the transformer is connected to a pair of switching transistors, a first of which couples the winding across B+ during a positive portion of the drive cycle, and a second of which couples a charged capacitor across the primary during a second, negative portion of the drive cycle. The duty cycle defined by the positive and negative portions of the cycle varies. In order to prevent excess current during saturation of the core for duty cycles other than 50%, the capacitor is sized to supply only enough voltage and current to reset the core.
    Type: Grant
    Filed: June 24, 1987
    Date of Patent: September 27, 1988
    Assignee: General Electric Company
    Inventor: Emilio F. D'Ariano
  • Patent number: 4772810
    Abstract: A high efficiency non-dissipative snubber circuit suitable for most power supplies used in international markets is disclosed. Circuit uses diode-capacitor-inductor structure to capture input voltage equivalent and reverse polarity on snubber capacitor. No external voltage source is required.
    Type: Grant
    Filed: September 30, 1986
    Date of Patent: September 20, 1988
    Assignee: Hewlett-Packard Company
    Inventor: Jimmie D. Felps
  • Patent number: 4771187
    Abstract: A bistable circuit comprises a flip-flop including at least one clock input, and a plurality of data inputs at least one of which is supplied with a signal at a timing independent of clocks applied to the clock input. The flip-flop also includes first and second outputs. First and second insulated gate field effect transistors are series-connected between the first output of the flip-flop and a predetermined voltage terminal. The first transistor is connected to receive at its gate a signal indicative of the condition of a selected one of the two outputs of the flip-flop, and the second transistor is connected to receive at its gate a control signal. When the selected one of the outputs assume an intermediate voltage, the first transistor is rendered conductive. In addition, the second transistor is rendered conductive in response to the control signal.
    Type: Grant
    Filed: May 19, 1986
    Date of Patent: September 13, 1988
    Assignee: NEC Corporation
    Inventor: Fumito Kawamura
  • Patent number: 4769558
    Abstract: A clock bus system fabricated on an integrated circuit for distributing a train of clock pulses to circuit elements on the integrated circuit. An input terminal is connected to receive a train of clock pulses. All of the circuit elements are circumscribed by a clock bus which is also coupled to each of the circuit elements. A plurality of distribution legs which include clock bus drivers are coupled to the input terminal by conductors and provide the train of clock pulses to the clock bus at spaced-apart locations. The distribution legs coupled to the input terminal by shorter conductors include delay elements for delaying the clock pulse train by time periods corresponding to the delay inherent in longer conductors. The clock pulse trains provided to the clock bus by the distribution legs are thereby synchronized with respect to each other.
    Type: Grant
    Filed: July 9, 1986
    Date of Patent: September 6, 1988
    Assignee: ETA Systems, Inc.
    Inventor: Randall E. Bach
  • Patent number: 4769560
    Abstract: An additional p-n junction diode, having a forward bias voltage smaller than a forward bias voltage between the base and emitter of a first-stage specific transistor of 3-stage Darlington connected npn transistors, is electrically connected in parallel between a p-type base layer and an n-type collector layer of the specific transistor. The polarities of the p-type and n-type layers of the diode are respectively the same as those of the parallel-connected p-type base and n-type collector layers of the specific transistor.
    Type: Grant
    Filed: February 12, 1987
    Date of Patent: September 6, 1988
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Keizo Tani, Junichi Nakao, Eiji Kotani
  • Patent number: 4767952
    Abstract: A circuit for high speed control a field effect power transistors. This circuit has a transformer with a primary winding and a secondary winding. The secondary winding transmits control signals to gates of the field effect power transistors. An energy storage structure is coupled to the transformer, and stores energy required for controlling the gates of the field effect power transistors. This energy is stored during an inactive phase of the control signal. A transmission structure is coupled to the transformer, and is fed with energy stored in the energy storage structure. In this way, the transmission structure uses energy stored in the energy storage structure to supply the control signals to the gates of the field effect power transistors. Therefore, the secondary of the transformer is not loaded during this time. At other times, the transmission structure isolates the output of the transformer from the rest of the circuit.
    Type: Grant
    Filed: December 3, 1986
    Date of Patent: August 30, 1988
    Assignee: Thomson-Lgt Laboratoire General des Telecommunications
    Inventor: Michel Nollet