Abstract: A circuit for detecting the variation of resistance of a variable-resistance element comprises a pair of grounded-base transistors with their base electrodes provided with different base voltages and with their emitter electrodes connected to both terminals of the variable-resistance element so that the voltage between both terminals of the element is kept constant. The current density of the variable-resistance element does not vary when the resistance of the variable-resistance element varies, whereby the lifetime of the element can be prolonged.

Abstract: A logarithmic compression circuit comprising an operational amplifier and a transistor for logarithmic compression. One of the emitter and collector of the transistor is connected to the inverting input of the amplifier and the other of the emitter and collector of the transistor is connected to the output of the amplifier. A switching device is selectively connected between the base of the transistor and the non-inverting input of the amplifier and between the base and the said one of the emitter and collector of the transistor in accordance with the magnitude of a signal current input.

Abstract: A circuit arrangement (13) for monitoring power supplies in N-channel CMOS devices, comprising elements for sampling of a bandgap voltage reference quantity (41), comparing the reference quantity to a monitored power supply voltage level (38), and compensating (49) for the offset voltage produced in the comparator element (31) conducting the comparison.

Abstract: The opening and closure of the contacts of a push-button actuated switch duces across impedance means a voltage which is stably high and low when such contacts are maintained closed and open, respectively. Bouncing of the contacts after their initial closures and openings produces superposition on the stable levels of such voltage of trains of impulses caused by such bouncing. A bistable semiconductor flip-flop is coupled to the impedance means to sense such voltage and to assume a "high" state and a "low" state only when the stable level of such voltage is, respectively, high and low and, further, the flip-flop receives a clock signal. A retriggerable semiconductor monostable multivibrator is coupled to such impedance means to be triggered by such impulses from its stable "off" state to its unstable "on" state which is repetitively renewed by repetitive retriggering of the multivibrator.

Abstract: A system for printing dot-matrix characters wherein a double column of dot forming elements is used, and no single dot forming element is required to print more often than once in any four column interval of printed text. Means for timing the actuation of the dot forming elements wherein the "on" time of the individual actuators can be longer than the time interval between columns is included.

Abstract: An RF switch employing a PIN diode as the switching element includes a first bias circuit providing forward dc current through the diode to enable RF transmission therethrough, and a second bias circuit providing reverse dc voltage across the diode to disable RF transmission through the switch. Status circuitry monitors the switch for failure modes of the diode, and control circuitry selectively enables the bias circuits. A short circuit failure of the PIN diode is indicated by the flow of reverse current in the second bias circuit in excess of the diode leakage current. Under this condition, the reverse current is latched by a thyristor in the second bias circuit and the status circuitry generates an alarm signal to the control circuitry inhibiting further selection of the first bias circuit. Optical couplers provide electrical isolation of the first and second bias circuit from the control and status circuitry.

Abstract: A circuit arrangement for retaining a main transistor in a conductive state while receiving an external turn-on control signal and bringing the main transistor to a complete cut-off state in response to an external turn-off control signal includes a circuit provided on the primary side of a transformer for supplying a turn-on signal or turn-off signal to the main transistor in response to the turn-on or turn-off control signal and a constant current circuit for maintaining the transformer primary current constant so that the currents derived from the turn-on and turn-off signals are kept constant.

Abstract: A variable impedance driver network comprises a plurality of transmission gates connected in parallel between a voltage source and an output. Each transmission gate has a predetermined nominal impedance and by turning on selective gates the overall impedance of the network may be adjusted to match that required at the output.

Abstract: A first npn transistor 4 becomes conductive when its input is at a first potential, and non-conductive when the input signal is at a second potential. A second npn transistor 6 is connected between an output terminal 7 and a low potential source 8; the base of the second transistor is connected to the collector of the first transistor. A Darlington circuit consists of third and fourth npn transistors 9 and 16a. The base of the third transistor is connected to the collector of the first transistor, and the collector of the third transistor 9 is connected to a high potential source 3. The emitter of the fourth transistor 16a is connected to the output terminal 7. The anode of a Schottky barrier diode 16b is connected to the base of the fourth transistor 16a, and the cathode of the Schottky barrier diode 16b is connected to the collector of the fourth transistor 16a.

Abstract: A solid state dc switch for switching power from the positive terminal of a ground referenced dc voltage source to the terminal of a ground referenced load. The solid state switch has a divide-by-two circuit means responsive to a clock signal and to a control signal first state for providing first and second symmetrical output signals at a frequency of one-half the frequency of said clock frequency. It also has a transformer drive and rectifier means for providing an isolated dc signal. An isolated switching means is included which is responsive to the high state of an isolated dc signal, having a transistor switch having a collector, an emitter and a base, the collector being coupled to a positive terminal of a ground referenced voltage source. The emitter is coupled to the return of the ground referenced load. The base is coupled to an isolated dc signal.

Abstract: An a.c. switch has two pairs of diodes each of which has two diodes connected in back-to-back relationship between the signal input and output of the switch. The two pairs of diodes are connected in parallel with each other in opposite senses. A MOSFET transistor is connected between the junctions of the two diodes in each pair. A switching control unit controls switching of the transistor such that, when the transistor is conducting, signal current flows between the input and output via one diode in one pair, the transistor, and one diode in the other pair. When the transistor is not conducting, current flow between the input and output is blocked.

Abstract: A programmable interval timer (100) for generating an error signal when a timing signal is received outside a predetermined time frame. The timer includes a timer circuit (104) having programmable minimum and maximum timing intervals for determining the predetermined time frame. These timing intervals are programmed into the timer circuit in response to data input signals indicative of the timing intervals from, for example, a microprocessor. The timer circuit generates one output signal when the time interval between two consecutively received timing signals is less than the minimum timing interval. Another output signal is generated when the time interval is greater than the maximum timing interval. An error signal latch generates the error signal when it receives either one of the two timer circuit output signals. Also included is a lock circuit (102) for preventing the timer circuit from responding to any data input signals after the first timing signal is received.

Abstract: A rectifier circuit is disclosed in which the levels of an input signal and a reference signal are compared, and the polarity of the equivalent resistor is set at positive or negative depending on the result of the comparison. The equivalent resistor is connected, as an input resistor, to a differential amplifier. A feedback resistor is connected between the input and output of the differential amplifier. This arrangement enables the rectifier circuit, with only a single differential amplifier, to perform the rectifying operation with a gain.

Abstract: A precharging circuit employing ordinary enhancement (E) types MIST'S produces erasing and writing (E-W) voltages to change the data stored in an EEPROM fabricated in a common memory chip with the circuit. The E-W voltage increases gradually from a low level to a high level over a long time interval determined substantially by a long time constant RC circuit, the voltage charge developed on the capacitor C comprising the E-W voltage. The resistor R is implemented by a first MIST connected between a high voltage source and the capacitor C, the gate thereof being controlled by a charge-pump (CP) circuit and a second MIST. The CP circuit is connected between the capacitor C and the gate of the first MIST and is rendered operative during successive clock pulses of a series of clock pulses applied thereto. The CP circuit, during each clock interval, produces a voltage output applied to the first MIST which exceeds the threshold voltage V.sub.

Abstract: A clocking pulse generator includes means for receiving voltage from a multi-phase alternating current electrical power source. A vector summing circuit provides a non-zero resultant vector for various combinations of multi-phase operating conditions. A multi-phase voltage dividing circuit couples the receiving means to the vector summing circuit. The non-zero resultant vector is converted into a halfwave rectified signal and applied to a first input of a comparator. The second input of the comparator is coupled to receive a preset threshold voltage. The comparator generates an output which provide clocking pulses therefrom.

Abstract: A monolithically integrated control circuit for the switching of transistors includes a control circuit coupled to a switching signal source. Signals from the signal source cause control circuit to switch at least one transistor connected thereto. The control circuit includes a current generated circuit designed to supply the at least one transistor with a high current. A current limiting circuit, actuated with a predetermined delay with respect to a turn-on cntrol signal used to switch the at least one transistor, limits the current supplied from the current generator circuit to the minimum level required to keep the at least one transistor at a conduction level which has been reached.

Abstract: An integrated circuit for emitting a clock voltage V.sub.A which alternates between positive and negative voltage levels with the clock voltage being controllable by means of a unipolar clock voltage V.sub.E and wherein the circuit is a very simple small semiconductor arrangement which has three series connected field effect transistors T1, T2 and T3 with the first end of the series arrangement receiving a first reference voltage and the other end of the series arrangement receiving a second reference voltage. The first and second field effect transistors 1 and 2 or first and second channel types and have gate terminals which are commonly connected to the control input V.sub.E and the junction point 3 of the first two field effect transistors T1 and T2 connected to the output terminal and also connected by way of a capacitor to the gate of the third field effect transistor T3 which is of the first channel type.

Abstract: A circuit for switching current in an inductive load comprising at least one semiconductor switch which periodically switches the current through the load by means of its main current path which is switched alternately to the conductive and to the non-conductive state. A voltage-limiting element for limiting the voltage occuring at it is connected parallel to this main current path. Voltage peaks occuring in the non-conductive state across the main current path are reduced in that the voltage-limiting element (10,11) has a resonance having an oscillation period which is at most approximately 2/3 of the time interval (tn) in which the main current path is non-conducting.

Abstract: A transducer means for sensing the movement of a component between first and second extreme positions includes a transducer 18 the output of which is applied to one input terminal of a differential amplifier. The output of the amplifier is applied to one input of a comparator at the output of which appears the output signal. The other input of the comparator is a voltage obtained from a resistor chain connected to the outputs of first and second sample and hold circuits the first of which is connected to the output of the differential amplifier and the second of which is connected to a peak hold circuit. The other input of the differential amplifier is connected to an integrator which integrates the signal provided by the first sample and hold circuit.

Abstract: A solid state relay circuit for switching power to an electrical load including an N-channel MOS-FET (20) having a drain (22) and source (24) and gate (26) terminals with the drain terminal (22) connected to the positive power supply lead (16) and the source terminal (24) connected to the load lead (12). The MOS-FET (20) is driven into conduction by being supplied voltage from a voltage multiplier (28-34) which is in turn supplied by a gated oscillator (36) which receives its power from an amplifier (38). Resistors (74, 76) may be added for slowly allowing the MOS-FET (20) to move into full conduction and/or for slowly decreasing the conduction of the MOS-FET. All this is in response to an electrical signal on a low level signal input lead (18).