Abstract: A circuit for high speed control a field effect power transistors. This circuit has a transformer with a primary winding and a secondary winding. The secondary winding transmits control signals to gates of the field effect power transistors. An energy storage structure is coupled to the transformer, and stores energy required for controlling the gates of the field effect power transistors. This energy is stored during an inactive phase of the control signal. A transmission structure is coupled to the transformer, and is fed with energy stored in the energy storage structure. In this way, the transmission structure uses energy stored in the energy storage structure to supply the control signals to the gates of the field effect power transistors. Therefore, the secondary of the transformer is not loaded during this time. At other times, the transmission structure isolates the output of the transformer from the rest of the circuit.

Abstract: Control power for driving semiconductor power components is transmitted by means of a pulse sequence. The same pulse sequence also contains the control information which has been impressed thereon by modulation. During transmission, the potentials of the control power and control information are separated by a transformer. The pulse sequence is subsequently rectified and demodulated after the potential-separated transmission. The recovered control information is then delivered to the components after demodulation.

Abstract: A detection circuit detects the ON-stage of the transistor at the post-stage of the output circuit. A base current-supply circuit is switched to the ON-state, according to the detection output of the detection circuit, so that a current is supplied from the supply-circuit to the base of the transistor at the pre-stage of the output circuit.

Abstract: A switching control circuit for a power transistor is provided. For applying an initial negative base current for disabling of the power transistor, a capacitor is provided which stores the energy required by charging not only when the power transistor is enabled but also when it is disabled. The capacitor discharges through a circuit for a time fixed by the time constant of a series RC network; this time is chosen of the order of time required for destoring the charges of the power transistor.

Abstract: A circuit device is provided for feedback controlling a transistor to switch off which is incorporated to a transfer circuit as the last stage thereof, and when, during the "off" phase, a current is drawn through its base by another transistor, referred to as the switch-off transistor, which is conductive for just the time required for said switching off to take place.

Abstract: A voltage controlled, triggered oscillator includes a NAND gate and a set of series connected triggerable delay circuits, the output of the NAND gate being fed back to one of its inputs through the delay circuits. A trigger signal is applied to another input of the NAND gate and to triggering inputs of the delay circuits. When the trigger signal is asserted, each delay circuit produces an output signal of state which tracks the state of its input signal but with a predetermined delay so that the NAND gate output oscillates with a frequency determined by the delay times of the delay circuits and the propagation time of the NAND gate. When the trigger signal is deasserted the NAND gate output is terminated and each delay circuit drives its output signal high regardless of the state of its input signal so that the oscillator may be rapidly retriggered.

Abstract: A circuit (FIG. 4) in which a sub-circuit comprised of a bias transistor (T1), a feedback reisistor (R2) connected between the collector of this transistor (T1) and its base, and, a drive transistor (T2), is connected to its polarity-inverse sub-circuit (T1', R2', T2') in a ring configuration and is initiated by means of current injection from a start-up bias circuit. The latter may comprise a bias transistor (T1"), a drive transistor (T2") the base of which is connected to the collector of the bias transistor (T1"), and a pair of feedback current/voltage divider resistors (R1", R2") in the collector path of the bias transistor (T1"). Following start-up, constant current is maintained by feedback in the ring, and this current may be tapped at an appropriate point in the ring.

Abstract: An integrated circuit switch including a Hall element, a Hall-voltage amplifier having an output to which the inputs of two Schmitt trigger circuits are connected may be mounted between stator windings in a brushless D.C. motor as a rotor position detector and motor commutator circuit. The outputs of the respective Schmitt trigger circuit may be connected to excite a pair of the stator windings. The two binary exciting signals are mutually complimentary except for having non-simultaneous changes from one binary state to the other. Integrated circuits of this invention eliminate acoustic noise that is caused by such overlapping stator currents that were unwittingly present in commutation circuits of the prior art.

Abstract: A line driver circuit capable of operating at high speeds. The output transistor, an emitter connected to an output terminal, has a special feedback capacitor connected to its base. The feedback capacitor helps pull the output terminal high to increase the switching speed of the line driver circuit. Special current injection and removal techniques are used to speed the switching times of the PNP current supply transistors. The line driver circuit also has special circuitry to limit the output current from exceeding certain limits and for keeping the line driver circuit from overheating.

Abstract: A linear Hall effect integrated circuit in which the output signal of a Hall element formed in an epitaxial layer is amplified by an amplifier circuit whose gain is determined by a resistor partially formed in the same epitaxial layer. A first amplifier stage configured as a voltage to current converter is connected through a current mirror to a second amplifier stage configured as a current to voltage converter. The current bias for the first amplifier stage is controlled by a resistor also partially formed in the epitaxial layer.

Abstract: A Detector Log Video Amplifier (DLVA) comprising a first RF detector for detecting the power levels of received RF signals having power levels within a first range (e.g., -40 dBm to -20 dBm) and producing corresponding first video frequency signals having amplitudes representative thereof, from which are produced output signals having amplitudes logarithmically proportional to such received signals. A second RF detector detects the power levels of received RF signals having power levels within a second range (e.g., -20 dBm to +20 dBm) and produces corresponding second video frequency signals having amplitudes representative thereof, from which are produced output signals having amplitudes logarithmically proportional to such received signals. A control signal is produced from the second video frequency signals, the control signal having a level in accordance with the power levels of received RF signals. Received RF signals having power levels equal to or exceeding a first level (e.g.

Abstract: A circuit for compensating the temperature dependence of gate propagation times includes a signal input for feeding-in an input signal; a signal output for issuing an output signal; a multiplexer having an output connected to the signal output and three inputs; a delay gate connected between one of the inputs of the multiplexer and the signal input, another of the inputs of the multiplexer being directly connected to the signal input; and a control input connected to a further one of the inputs of the multiplexer for controlling the multiplexer in dependence on temperature and feeding the input signal to the signal output delayed in a lower temperature range, undelayed in an upper temperature range and mixed, delayed as well as undelayed in a temperature range therebetween.

Abstract: A pulse generator circuit includes (a) a delay circuit responsive to an input signal for producing an output signal after a predetermined delay time, (b) a first logic circuit responsive to the input signal and this output signal for producing an output signal having a first logic state when both of the input signal and the output signal from the delay circuit are concurrently of a second logic value, (c) a second logic circuit responsive to the input signal and the output signal from the delay circuit for producing an output signal having the first logic state when both the input signal and the output signal from the delay circuit are of the first logic value, and (d) a third logic circuit responsive to the output signal from the first logic circuit and to the output signal from the second logic circuit for producing an output signal having a first logic state when both of the output signal from the first logic circuit and the output signal from the second logic circuit are concurrently of the second logic v

Abstract: An integrated anode power stage using one or more Darlington transistors combinations is constituted for currents exceeding 5 amperes and voltages exceeding 200 volts. On a common semiconductor substrate there are provided, in addition to the Darlington circuit or circuits a large number of peripheral components, both active and passive, such as are required for protection, regulation and turning on or off of the final stage for operating an ignition coil in a motor vehicle. By providing these components in basins of the same conductivity type as the base of the power transistor a unit is provided that is economical to make as well as compact and reliable.

Abstract: A high voltage bidirectional output semiconductor field effect transistor (BOSFET) is disclosed which is turned on from the electrical output of a photovoltaic stack which is energized from an LED. The process for manufacture of the device is also disclosed. The BOSFET device consists of two lateral field effect transistors formed in an implanted N(-) region in a P(-) substrate. Two spaced drain regions feed inwardly toward a common N(+) source region separated from the drains by respective P type diffusions. The surface of these diffusions can be inverted by application of voltage to the suitably disposed gate electrode. The depletion field between channel and drain regions is well controlled over the surface of the device. The source contact remains close to the potential of the gate contact at all times so that the device can be used for high voltage switching of either polarity.

Abstract: A solid state relay comprises a light-emitting diode (2) for generating radiation in response to forward current supplied thereto and an array (5) of photodiodes optically coupled to the light-emitting diode for generating a voltage in response to radiation from the light-emitting diode. A thyristor (18) is provided having anode and cathode coupled to the gate and substrate electrodes (11a, 11b, 14a, 14b) of a field-effect transistor, respectively. A gate electrode (21) of the thyristor is connected to one end (7) of the photodiode array (5) and the cathode of the thyristor is further connected to the other end (8 ) of the photodiode array. The voltage generated by the photodiode array is applied to the switching transistor (9, 10) through a diode (17) so that the impedance between the source and drain electrodes of the transistor has a low value in the presence of the voltage and a high value in the absence of the voltage.

Abstract: High voltage is connected and disconnected in less than a microsecond from a high voltage power supply to a radar transmitter using a solid state relay. The solid state relay supplies this high voltage using multiple power MOSFETs, which are serially-connected between the source and the load. The gate of each power MOSFET is simultaneously triggered by trigger circuits which, in turn, are activated and coupled by a single turn transformer. The transformer is driven by a pair of field effect transistors, which are activated by a pair of open collector comparators. The open collector comparators only activate when they receive a signal indicating that the radar transmitter should transmit a waveform.

Abstract: A DC coupled transistor turn-off circuit (12) responsive to a first DC voltage level for reverse driving the base of an output transistor (Q4), and responsive to a second DC voltage level for removing the reverse base drive. A turn-off transistor (Q5) is connected to the base (22) of the output transistor (Q4) for reverse driving it, and another transistor (Q6) is connected to the turn-off transistor (Q5) for turning it off. A pair of diodes (32, 34), each with different forward voltage drops, are connected between the respective bases of the turn-off circuit transistors (Q5, Q6) and a circuit input node (16). When the rising edge of the input voltage at such node reaches the first DC level, the first diode (32) conducts and activates the turn-off transistor (Q5) which reverse drives the base of the output transistor (Q4).

Abstract: A latch circuit including an input logic network that incorporates emitter-coupled logic switching arrangements connected in multiple levels to perform logical operations on the received input signals. The latch circuit is controlled by differential clock signals coupled to a differential switch circuit that is connected to the input logic network to form another switch level. An output buffer is connected to the input logic network to generate output signals of selected logic voltage levels. When the differential clock signals are in a pass condition, the input logic network is enabled to transmit an output signal to the output buffer. When the differential clock signals are in a latch, or hold, condition, the input logic network is disabled and a feedback network is enabled to maintain the signal to the output buffer in the conditions it was in when the differential clock signals changed conditions.

Abstract: A device for magnetic pulse treatment of ferromagnetic materials applicable in the engineering industry and used for changing the physicomechanical properties of materials treated, treats the material in a winding, positive potential being fed from a supply unit across a controllable switch to the anodes of first diodes and cathodes of second diodes which are energized. Capacitors then are charged to the voltage of the supply source for the time for which controllable switch is on. Then at different time intervals control pulses are fed to controlling thyristor electrodes. One capacitor discharges across the winding and energized thyristor; current in specific direction running across the winding. Then, the other capacitor and thyristor discharge and current of opposite direction runs across the winding, thus forming a bipolar pulse magnetic field affecting the material physical and mechanical properties, the magnetization and demagnetization running for about 1 minute.