Abstract: A circuit receives either a composite voltage, which is the sum of a signal voltage and a noise voltage, or the noise voltage. A switching arrangement is used to charge a first capacitor to the composite voltage, and a second capacitor to the noise voltage. The opposite poles of the first and the second capacitors are connected after they are charged, to generate an output voltage which is proportional to the signal voltage alone.

Abstract: A bootstrap condenser connected to the output of the circuit is preloaded during the low output state when the load transistor is off and the drive transistor is normally on. A commutation signal brings about extinction of the drive transistor and connection of the condenser to the gate of the load transistor to turn on the latter and secure the resulting rise of the circuit output. Transistors of the pilot circuit are arranged for maximum bootstrap efficiency.

Abstract: In a multi-level ECL series gating circuit with three levels of gating which operates over specified operating circuit voltage and operating circuit temperature ranges, provision is made for stabilizing the magnitude of the circuit source current over the operating voltage and temperature ranges by regulating the bias voltage which determines the circuit source current. The bias voltage is regulated according to the inverse of the operating temperature to account for the temperature characteristics of the base-to-emitter diode in the transistor generating the circuit current. The magnitude of the bias voltage over the temperature range never reaches a level which will send the circuit current transistor into saturation at any circuit voltage in the operating range.

Abstract: An ECL circuit comprising an output transistor having a base, a resistor coupled to the base, a first circuit responsive to a deselect signal OE for drawing a first current through the resistor and a second circuit responsive to the deselect signal OE for drawing a second current through the resistor, said first and said second currents combining in said resistor for providing a predetermined turn-off bias potential on said base of said output transistor. The predetermined turn-off bias potential reduces the emitter current of the output transistor such that the noise immunity of a data bus is preserved when a plurality of output transistors are coupled in parallel to the data bus.

Abstract: A complementary Bi-MIS gate circuit including two CMIS circuits each having a PMIS transistor connected to a high potential source, an NMIS transistor connected to a low potential source, and an impedance element connected between the PMIS and NMIS transistors, and a load driving inverter having a vertically structured pull-up bipolar transistor and a vertically structured pull-down bipolar transistor connected in series. The base terminals of the pull-up and pull-down bipolar transistors are connected to a high voltage level end of the impedance element in one CMIS circuit and to a low voltage level end of the impedance element in the other CMIS circuit respectively. The input signal for the gate circuit is fed to the gate terminals of all the PMIS and NMIS transistors and the output signal of the gate circuit is produced at a connection point between the pull-up and pull-down bipolar transistors.

Abstract: A driving circuit uses an output transistor and a driving transformer with a secondary coil being connected to the base of the output transistor. In order to get a high speed switching circuit without thermal runaway, the storage period of the output transistor is detected. A signal supplied to a primary coil of the driving transformer, for example, a driving pulse, is controlled in response to the detected value of the storage period. By minimizing the value of the storage period, it becomes possible to minimize a fall time of the output transistor, so that a stability of the driving circuit can be maintained.

Abstract: An improved driver interface circuit for interfacing between low voltage, low drive capability logic signals and large capacitive loads requiring high speed, high voltage logic signals. The improvement comprising the use of the logic input signal to power gate a high level buffer contained in the driver and thereby minimize the power consumption during inactive periods.

Abstract: A saturation condition regulator system for a power transistor which achieves the regulation objectives of a Baker clamp but without dumping excess base drive current into the transistor output circuit. The base drive current of the transistor is sensed and used through an active feedback circuit to produce an error signal which modulates the base drive current through a linearly operating FET. The collector base voltage of the power transistor is independently monitored to develop a second error signal which is also used to regulate base drive current. The current-sensitive circuit operates as a limiter. In addition, a fail-safe timing circuit is disclosed which automatically resets to a turn OFF condition in the event the transistor does not turn ON within a predetermined time after the input signal transition.

Abstract: Disclosed is a power source reset circuit which deactivates a contactless switch for a time interval determined by a delay means so as to prevent any erroneous output from the contactless switch while the output of a power source is unstable immediately after the power source is turned on. The reliability of the delay means is enhanced by the use of a Miller integration circuit which includes a current mirror circuit as a means for amplifying electric current. Furthermore, a switching device may be connected across the capacitor for integration so that the charge in the capacitor may be quickly discharge when the power is turned off, for the purpose of setting the power source reset circuit ready for the subsequent action when the power source is turned on thereafter. This invention is useful in applications where the power source for the contactless switch is frequently turned on and off.

Abstract: A MOSFET gate driver circuit reduces the noise susceptibility of a MOSFET switch by utilizing dual drive paths to apply turn-on and turn-off bias signals to the gate of the MOSFET. Drive pulses are coupled to the MOSFET switch via a pulse transformer which has two serially connected secondary windings. Turn-on pulses are coupled by a diode from the first secondary to the MOSFET gate. Turn-off pulses are coupled via the second secondary to a control MOSFET which is turned on by a turn-off pulse and remains on in order to keep the gate of the MOSFET switch to a hold off voltage.

Abstract: The invention concerns a process for control of the opening of a power interrupter, especially a transistor, at a determined instant, regardless of the particular characteristics of the interrupter. According to the invention, the emission of the normal closing command (A) of the interrupter is terminated at a determined time interval before the said determined instant, and in its place is emitted an additional closing command (G) with a duration equal to the difference between the said interval and the actual time required by the interrupter to pass from the closed state to the open state. Preferably, the actual time required by the interrupter to change state is determined during its preceding passages from the closed state to the open state.

Abstract: A delay circuit which is insensitive to variations in power supply voltage, which is temperature-compensated, and which is suitable for fabrication in a monolithic integrated circuit includes circuitry for charging a capacitive element through a resistive element from GND toward the power supply voltage. The voltage across the capacitive element is compared to a reference voltage by a voltage comparator, and the voltage comparator generates an output signal when the voltage on the capacitor becomes greater than the reference voltage. The reference voltage for the comparator is generated by a resistor divider connected between GND and the power supply voltage. Inasmuch as the reference voltage varies with changes in the power supply voltage in such a manner as to be maintained at a substantially fixed percentage of the power supply voltage, the time delay provided by the delay circuit is essentially independent of variations in power supply voltage.

Abstract: A semiconductor device comprising first and second transistors connected in series with one another to pass a primary current upon receipt of a control signal at the gate of the second transistor. The first transistor is coupled to receive a base current from a secondary power source. A third transistor is coupled to have a current path shunt that base current away from the first transistor upon conduction of the third transistor. A control electrode of the third transistor is coupled to receive the control signal also received at the gate of the second transistor. The polarity of the third transistor is selected to render the third transistor conductive when the second transistor is rendered non-conductive in response to the control signal and to render the third transistor non-conductive when the second transistor is rendered conductive by the control signal.

Abstract: A switching circuit for and inductive load with a parallel freewheeling diode comprises a semiconductor switch in series therewith across a power supply and a switch control effective to change the semiconductor switch from a nonconducting to a conducting state by sourcing current to the control electrode to charge the internal capacitance. The switch control means is responsive to the load voltage to produce a lower current rate to the control electrode while the load voltage indicates a condition other than reverse bias for the freewheeling diode in order to reduce RFI by slowing the switching of the semiconductor switch while the freewheeling diode is recovering and a higher current rate as soon as the load voltage indicates reverse bias for the freewheeling diode in order to minimize time spent in the active conduction region of the semiconductor switch and thus minimize resultant heat generation during switching.

Abstract: An ECL circuit comprising an output transistor having a high output voltage VOH guard band and a low output voltage VOL guard band with a temperature compensating network coupled to the output transistor for causing the high level output voltage VOH and low level output voltage VOL of the output transistor to remain within the maximum and minimum limits of the VOH and VOL guard bands over a wide temperature range.

Abstract: A high-voltage FET pulser for a synthetic aperture radar transmitter includes an FET ON switch and a tail biter switch both on the floating deck and coupled to a pulse driver circuit through a transformer having a quartz glass tube isolating the secondary winding from the core and primary winding. An active shunt regulator circuit is connected to the output of the FET ON switch to provide a flat output pulse free of ringing.

Abstract: A diode network includes a series branch coupled between two signal ports and a shunt branch coupled between a node in the series branch and ground and connected in parallel with a transistor of a latching circuit that is further coupled to supply forward bias to the shunt branch and reverse bias to the series branch when the transistor is conductive for blocking RF signal flow between the ports. The bias applied to the branches is reversed when the latch transistor is non-conductive thereby enabling RF signal flow between the ports. The transistor provides plural functions of establishing positive feedback for the latch, supplying forward and reverse bias to the shunt and series branches, respectively, and enhancing the attenuation of the shunt branch when conductive.

Abstract: A high efficiency switching circuit, which may be monolithically integrated, includes a power output transistor which is driven to switch by means of a second transistor coupled to its control terminal. Circuit components for charge extraction are connected to the base terminals of both transistors and are activated by an enabling circuit having a control terminal and an input terminal connected to the collector terminal of a third transistor having its emitter and base terminals respectively connected to the emitter terminal and the base terminal of the second transistor.

Abstract: A JFET circuit generates an adjustable current having a temperature coefficient proportional to I.sub.DSS where I.sub.DSS is the drain current of a JFET when its source and gate are shorted. The JFET has a source terminal coupled to a source of supply voltage. An adjustable resistor is coupled between the gate and source terminals of the JFET. A reference current is supplied to the resistor, which reference current is proportional to the JFET's pinch-off voltage. The desired current appears at the drain of the JFET.

Abstract: To a carrier (1, 1') there is cemented a bar of a material (3, 3'), for example glass or a ceramic material, which is subsequently divided, using cuts (7, 7') which extend transversely of its longitudinal direction, into a number of slices (9, 9') which are separately cemented to the carrier. Each slice (9, 9') is provided with a groove (13, 13') which extends parallel to the cuts (7, 7'). The grooves (13, 13') are curved and have a center of curvature which is situated at the side of the bar (3, 3') which faces the carrier (1, 1'). In the grooves (13, 13') there are secured optical fibres (19, 19') which follow the curvature of the groove, after which a side portion of the fibres which is situated furthest from the carrier (1, 1') is ground off. A flat ground face (21, 21') is thus formed one each fibre (19, 19'). Such ground fibres (19, 19') are arranged so that their ground faces contact one another in order to form directional couplers, after which the slices (9, 9') are detached from the carrier (1, 1').