Abstract: Acene-thiophene compounds are disclosed that are useful as organic semiconductors. The compounds, when used as the semiconductor layer in organic thin-film transistors exhibit device characteristics, like charge-carrier mobilities and current on/off ratios, that are comparable to those of pentacene. Also described are semiconductor devices comprising at least one compound of the invention; and articles comprising the semiconductor devices such as thin film transistors or transistor arrays, and electroluminescent lamps.

Abstract: A MgO tunnel barrier is sandwiched between semiconductor material on one side and a ferri- and/or ferromagnetic material on the other side to form a spintronic element. The semiconductor material may include GaAs, for example. The spintronic element may be used as a spin injection device by injecting charge carriers from the magnetic material into the MgO tunnel barrier and then into the semiconductor. Similarly, the spintronic element may be used as a detector or analyzer of spin-polarized charge carriers by flowing charge carriers from the surface of the semiconducting layer through the MgO tunnel barrier and into the (ferri- or ferro-) magnetic material, which then acts as a detector. The MgO tunnel barrier is preferably formed by forming a Mg layer on an underlayer (e.g., a ferromagnetic layer), and then directing additional Mg, in the presence of oxygen, towards the underlayer.

Abstract: Structures and methods for in service programmable logic arrays with low tunnel barrier interpoly insulators are provided. The in-service programmable logic array includes a first logic and a second logic plan having a number of logic cells arranged in rows and columns that are interconnected to produce a number of logical outputs such that the in service programmable logic array implements a logical function. The logic cell includes a first source/drain region and a second source/drain region separated by a channel region in a substrate. A floating gate opposing the channel region and is separated therefrom by a gate oxide. A control gate opposes the floating gate. The control gate is separated from the floating gate by a low tunnel barrier intergate insulator. The low tunnel barrier intergate insulator includes a metal oxide insulator selected from the group consisting of PbO, Al2O3, Ta2O5, TiO2, ZrO2, Nb2O5 and/or a Perovskite oxide tunnel barrier.

Abstract: Prior to converting a non-single crystal material of a semiconductor film into a single crystal material through the use of a laser beam, at least one dopant is introduced into whole of the semiconductor film. Then, the non-single crystal semiconductor film is irradiated with a laser beam to crystallize the semiconductor film. In this case, a ratio between quasi-fermi level of the single crystal material within one of transistor formation regions used to form transistors of different conductivity types and quasi-fermi level of the single crystal material within the other thereof is made to be between 0.5:1 and 2.0:1. Thus, transistors of different conductivity types are formed in the crystallized semiconductor film.

Abstract: A semiconductor integrated circuit having a plurality of interconnect layers and at least one via connecting interconnects of two adjacent interconnect layers, wherein each interconnect layer has a plurality of first interconnect groups and second interconnect groups arranged respectively in a row and a column in a matrix. The first and the second interconnect groups are alternately arranged in each row and in each column of the matrix arranged facing each other between two adjacent interconnect layers. The first and second interconnect groups facing each other between the layers have crossing parts where they can be connected through vias.

Abstract: A method of fabricating a structure and fabricating related semiconductor transistors and novel semiconductor transistor structures. The method of fabricating the structure includes: providing a substrate having a top surface; forming an island on the top surface of the substrate, a top surface of the island parallel to the top surface of the substrate, a sidewall of the island extending between the top surface of the island and the top surface of the substrate; forming a plurality of carbon nanotubes on the sidewall of the island; and performing an ion implantation, the ion implantation penetrating into the island and blocked from penetrating into the substrate in regions of the substrate masked by the island and the carbon nanotubes.

Abstract: In a nitride semiconductor device according to one embodiment of the invention, a p-type gallium nitride (GaN) layer electrically connected to a source electrode and extending and projecting to a drain electrode side with respect to a gate electrode is formed on an undoped or n-type aluminum gallium nitride (AlGaN) layer serving as a barrier layer.

Abstract: A method of depositing dielectric material into sub-micron spaces and resultant structures is provided. After a trench is etched in the surface of a wafer, a silicon nitride barrier is deposited into the trench. The silicon nitride layer has a high nitrogen content near the trench walls to protect the walls. The silicon nitride layer further from the trench walls has a low nitrogen content and a high silicon content, to allow improved adhesion. The trench is then filled with a spin-on precursor. A densification or reaction process is then applied to convert the spin-on material into an insulator. The resulting trench has a well-adhered insulator which helps the insulating properties of the trench.

Abstract: The present invention comprises a method for forming a semiconducting device including the steps of providing a layered structure including a substrate, a low diffusivity layer of a first-conductivity dopant; and a channel layer; forming a gate stack atop a protected surface of the channel layer; etching the layered structure selective to the gate stack to expose a surface of the substrate, where a remaining portion of the low diffusivity layer provides a retrograded island substantially aligned to the gate stack having a first dopant concentration to reduce short-channel effects without increasing leakage; growing a Si-containing material atop the recessed surface of the substrate; and doping the Si-containing material with a second-conductivity dopant at a second dopant concentration. The low diffusivity layer may be Si1-x-yGexZy, where Z can be carbon (C), xenon (Xe), germanium (Ge), krypton (Kr), argon (Ar), nitrogen (N), or combinations thereof.

Abstract: A nonvolatile semiconductor memory device of a split gate structure having a gate of low resistance suitable to the arrangement of a memory cell array is provided. When being formed of a side wall spacer, a memory gate is formed of polycrystal silicon and then replaced with nickel silicide. Thus, its resistance can be lowered with no effect on the silicidation to the selection gate or the diffusion layer.

Abstract: Methods of forming thin film devices with different electrical characteristics on a substrate comprising a driver circuit region and a pixel region. A first and a second polysilicon pattern layers are formed on the driving circuit region and the pixel region of the substrate, respectively. A first ion implantation is performed on the second polysilicon pattern layer using a masking layer covering the first polysilicon pattern layer as an implant mask, such that the first polysilicon pattern layer has an impurity concentration different from the second polysilicon pattern layer. After removal of the masking layer, a gate dielectric layer and a gate are successively formed on each of the first and second polysilicon pattern layers and a source/drain region is subsequently formed in each of the first and second polysilicon pattern layers to define a channel region therein.

Abstract: A method of manufacturing flash memory devices, comprises the steps of forming an oxide film on a semiconductor substrate, performing a pre-annealing process under N2 gas atmosphere, nitrifying the oxide film by performing a main annealing process under N2O atmosphere having the flow rate of 5 to 15 slm for 10 to 60 minutes, thus forming an oxynitride film, and performing a post-annealing process under N2 gas atmosphere.

Abstract: An exemplary method for making a memory structure comprises forming a first ferromagnetic layer, forming a spacer layer above the first ferromagnetic layer, forming a second ferromagnetic layer above the spacer layer by applying a first deposition process to form a thin layer of ferromagnetic material substantially covering the spacer layer, the first layer being formed at a first energy level, and applying a second deposition process to form the remainder of the second ferromagnetic layer above the thin layer of ferromagnetic material, the second ferromagnetic layer being formed at a second energy level, higher than the first energy level. This way, the spacer layer is protected by the thin layer during the second energy level deposition.

Abstract: A semiconductor device formed on a silicon carbide semiconductor substrate comprises an epitaxial layer formed on a surface sloping (or inclining) by 0 to less than 1 degree from a (000-1) face of the silicon carbide semiconductor substrate, wherein at least one of a P type semiconductor area or an N type semiconductor area is selectively formed in the epitaxial layer by ion implantation, a metal electrode is formed so as to contact a surface layer of the P type semiconductor area or the N type semiconductor area, a rectification function is shown between the metal electrode and the P type semiconductor area or the N type semiconductor area, and the semiconductor device is formed on the silicon carbide semiconductor substrate of a Schottky barrier diode or a PN type diode.

Abstract: A field emission type cold cathode, comprising a substrate having a conductivity at least on the surface thereof, an insulation layer formed on the substate and having a first opening part, a gate electrode layer formed on the insulation layer, having a center generally aligned with the center of the first opening part, and having, therein, a second opening part having an opening diameter larger than the opening diameter of the first opening part, and an emitter layer formed in the first opening part, the emitter layer characterized by further comprising the bottom surface and the side surfaces of the first opening part.

Abstract: A method for manufacturing a ferroelectric memory includes: (a) forming first and second contact sections on a first dielectric layer formed above a base substrate; (b) forming a laminated body having a lower electrode, a ferroelectric layer and an upper electrode successively laminated; (c) forming a conductive hard mask above the laminated body and etching an area of the laminated body exposed through the hard mask, to thereby form a ferroelectric capacitor above the first contact section; (d) forming above the first dielectric layer a second dielectric layer that covers the hard mask, the ferroelectric capacitor and the second contact section; (e) forming a contact hole in the second dielectric layer which exposes the second contact section; (f) providing a conductive layer in an area including the contact hole for forming a third contact section; and (g) polishing the conductive layer and the second dielectric layer until the hard mask above the ferroelectric capacitor is exposed.

Abstract: A semiconductor memory device includes: a gate electrode formed on a semiconductor layer via a gate insulating film; a channel region disposed under the gate electrode; diffusion regions disposed on both sides of the channel region and having a conductive type opposite to that of the channel region; and memory functional units formed on both sides of the gate electrode and having the function of retaining charges, wherein each of the diffusion regions has: a high-concentration impurity region disposed so as to be offset from the gate electrode; and a low-concentration impurity region disposed in contact with the high-concentration impurity region so as to overlap with the gate electrode, and an amount of current flowing from one of the diffusion regions to the other diffusion region is changed when a voltage is applied to the gate electrode in accordance with an amount of charges retained in the memory functional units.

Abstract: A method and apparatus for an electronic substrate having a plurality of semiconductor devices is described. A thin film of nanowires is formed on a substrate. The thin film of nanowires is formed to have a sufficient density of nanowires to achieve an operational current level. A plurality of semiconductor regions are defined in the thin film of nanowires. Contacts are formed at the semiconductor device regions to thereby provide electrical connectivity to the plurality of semiconductor devices. Furthermore, various materials for fabricating nanowires, thin films including p-doped nanowires and n-doped nanowires, nanowire heterostructures, light emitting nanowire heterostructures, flow masks for positioning nanowires on substrates, nanowire spraying techniques for depositing nanowires, techniques for reducing or eliminating phonon scattering of electrons in nanowires, and techniques for reducing surface states in nanowires are described.

Abstract: A MFS type field effect transistor includes a semiconductor layer, a PZT system ferroelectric layer formed on the semiconductor layer, a gate electrode formed on the PZT system ferroelectric layer, and an impurity layer composing a source or a drain, formed in the semiconductor layer. The PZT system ferroelectric layer includes Nb that replaces a Ti composition by 2.5 mol % or more but 40 mol % or less.

Abstract: A mass of material is formed over a semiconductor substrate. Semiconductive material is formed laterally proximate the mass of material. A space is provided laterally between the mass of material and the semiconductive material. The space comprises an outermost portion and a portion immediately adjacent thereto. The outermost portion has a maximum lateral width which is greater than that of the adjacent portion. Gate dielectric material and conductive gate material are formed within the space. The gate dielectric material and the conductive gate material in combination fill the adjacent portion of the space but do not fill the outermost portion of the space. At least the conductive gate material is etched from at least a majority of the outermost portion of the space. Source/drain regions are formed operatively proximate the conductive gate material and the semiconductive material is used as a channel region of the field effect transistor.