Abstract: An isotropic-diffusion filling method uses a thermal process on a result structure comprising a photoresist layer and an organic material layer to create a cross-linking layer there between, which minimizes step height differences between isolated and dense via-pattern regions for optimizing a subsequent trench process and simplifying process steps.

Abstract: A scheme for aligning opaque material layers of a semiconductor device. Alignment marks are formed in a via level of the semiconductor device. The alignment marks are formed using a separate lithography mask, and may have about the same length as vias formed in the via layer. The alignment marks comprise trenches that are not filled with material and are not exposed to a CMP process. An opaque material layer is deposited, and depressions are formed in the opaque material layer over the alignment mark trenches. The depressions in the opaque material layer are used to align a lithography process to open the opaque material layer over alignment marks in an underlying metallization layer. The alignment marks in the metallization layer are then used to align the lithography process used to pattern the opaque material layer.

Abstract: A method for forming a modified semiconductor having a number of band gaps involves providing a semiconductor having a surface and a quantum region which emits photons in response to electrical or optical stimulation, the quantum region having an original band gap and being disposed under the surface and applying a number of layers of a number of materials to a number of selected regions of the surface, the materials being adapted to cause, upon thermal annealing, a number of different degrees of intermixing in a number of portions of the quantum region disposed immediately below each of the selected regions of the surface. The layers of materials can be applied in a dot or line pattern, or both, to increase the plurality of band gap tuning. The method includes thermally annealing the layers to the surface.

Abstract: This invention discloses a process for forming durable anti-stiction surfaces on micromachined structures while they are still in wafer form (i.e., before they are separated into discrete devices for assembly into packages). This process involves the vapor deposition of a material to create a low stiction surface. It also discloses chemicals which are effective in imparting an anti-stiction property to the chip. These include polyphenylsiloxanes, silanol terminated phenylsiloxanes and similar materials.

Abstract: Disclosed herein is a method of forming a metal wiring of a semiconductor device.

Abstract: A substrate for mounting a semiconductor chip is formed as a multilayer substrate by alternately laminating insulation layers and wiring layers. Wires of the wiring layers are electrically connected through a via-hole for interlayer continuity. A through-hole provided through the insulation layer of the outermost surface layer is formed. A bump is inserted in the through-hole to a bump allocating position of the semiconductor chip to be mounted in the insulation layer of the outermost surface layer. A portion of the wire in the wiring layer of the outermost surface layer is projected to the internal side of through-hole at the aperture of the through-hole.

Abstract: Semiconductor laser diodes, particularly high power AlGaAs-based ridge-waveguide laser diodes, are often used in opto-electronics as so-called pump laser diodes for fiber amplifiers in optical communication lines. To provide the desired high power output and stability of such a laser diode and avoid degradation during use, the present invention concerns an improved design of such a device, the improvement in particular significantly minimizing or avoiding (front) end section degradation of such a laser diode and significantly increasing long-term stability compared to prior art designs. This is achieved by establishing one or two “unpumped end sections” of the laser diode. One preferred way of providing such an unpumped end section at one of the laser facets (10, 12) is to insert an isolation layer (11, 13) of predetermined position, size, and shape between the laser diode's semiconductor material and the usually existing metallization (6).

Abstract: A method for manufacturing a ferroelectric capacitor in accordance with the present invention includes: (a) a step of forming a ferroelectric laminated body by successively laminating a lower electrode layer, a ferroelectric layer and an upper electrode layer over a base substrate; (b) a step of patterning at least the upper electrode layer and the ferroelectric layer by dry etching; (c) a step of coating a coating composition including a compound having an element composing the ferroelectric layer at least on a side wall of the ferroelectric layer; and (d) a step of thermally treating the coating composition, to crystallize the coating composition coated on the side wall of the ferroelectric layer.

Abstract: An MTJ (magnetic tunneling junction) MRAM (magnetic random access memory) cell is formed on a conducting lead and magnetic keeper layer that is capped by a sputter-etched Ta layer. The Ta capping layer has a smooth surface as a result of the sputter-etching and that smooth surface promotes the subsequent formation of a lower electrode (pinning/pinned layer) with smooth, flat layers and a radical oxidized (ROX) Al tunneling barrier layer which is ultra-thin, smooth, and to has a high breakdown voltage. A seed layer of NiCr is formed on the sputter-etched capping layer of Ta. The resulting device has generally improved performance characteristics in terms of its switching characteristics, GMR ratio and junction resistance.

Abstract: A method for forming a transistor including a self aligned metal gate is provided. According to various method embodiments, a high-k gate dielectric is formed on a substrate and a sacrificial carbon gate is formed on the gate dielectric. Sacrificial carbon sidewall spacers are formed adjacent to the sacrificial carbon gate, and source/drain regions for the transistor are formed using the sacrificial carbon sidewall spacers to define the source/drain regions. The sacrificial carbon sidewall spacers are replaced with non-carbon sidewall spacers, and the sacrificial carbon gate is replaced with a desired metal gate material to provide the desired metal gate material on the gate dielectric. Various embodiments form source/drain extensions after removing the carbon sidewall spacers and before replacing with non-carbon sidewall spacers. An etch barrier is used in various embodiments to separate the sacrificial carbon gate from the sacrificial carbon sidewall spacers.

Abstract: A homojunction bipolar transistor with performance characteristics similar to more costly heterojunction or retrograde base transistors. The high emitter resistivity found in prior homojunction devices is circumvented using a low work function material layer in forming the emitter. This produces an economically viable high performance alternative to SiGe HBTs or SiGe retrograde base transistors.

Abstract: A SiGe heterojunction bipolar transistor including at least an emitter formed on a SiGe base region wherein the sidewalls of the emitter are protected by a conformal passivation layer. The conformal passivation layer is formed on the exposed sidewalls of said emitter prior to siliciding the structure. The presence of the passivation layer in the structure prevents silicide shorts from occurring by eliminating bridging between adjacent silicide regions; therefore improved SiGe bipolar yield is obtained. A method for forming such a structure is also provided.

Abstract: After an SiC film (4), an SiO2 film (5) and a silicon nitride film (6) are formed sequentially on an organic low dielectric constant film (3), by performing O2 plasma processing to a surface of the silicon nitride film (6), an oxide layer (7) is formed on the surface of the silicon nitride film (6). Then, a wiring trench pattern is formed on the silicon nitride film (6) and the oxide layer (7), and a resin layer (10) on which a via hole pattern is formed is formed. Subsequently, a portion of the oxide layer (7) exposed from the resin layer (10) is removed along with unnecessary particles.

Abstract: The present invention discloses a method for fabricating a pixel area of an electro-luminescent display device. At least one buffer layer is formed on a substrate. An etch stop layer is formed on the buffer layer. At least one intermediate layer is formed over the etch stop layer. The intermediate layer is etched to expose the etch stop layer, which has an etch rate substantially selective against that of the intermediate layer. The etch stop layer is etched to expose the buffer layer, which has an etch rate substantially selective against that of the etch stop layer, thereby improving an level uniformity of the exposed buffer layer.

Abstract: A CSTBT includes a carrier stored layer (113) formed between a P base region (104) and a semiconductor substrate (103) and the carrier stored layer has an impurity concentration higher than that of the semiconductor substrate (103). The P base region (104) in a periphery of a gate electrode (110) functions as a channel. When it is assumed that an impurity concentration of a first carrier stored layer region (113a) just under the channel is ND1 and an impurity concentration of a second carrier stored layer region (113b) other than just under the channel is ND2 in the carrier stored layer (113), the relationship of the impurity concentrations is defined by ND1<ND2. Thus, a gate capacity and a short-circuit current can be controlled and variation in threshold voltage can be prevented.

Abstract: A light emitting device which is capable of suppressing deterioration by diffusion of impurities such as moisture, oxygen, alkaline metal and alkaline earth metal, and concretely, a flexible light emitting device which has light emitting element formed on a plastic substrate. On the plastic substrate, disposed are two layers and more of barrier films comprising a layer represented by AlNxOy which is capable of blocking intrusion of moisture and oxygen in a light emitting layer and blocking intrusion of impurities such as an alkaline metal and an alkaline earth metal in an active layer of TFT, and further, a stress relaxation film containing resin is disposed between two layers of barrier films.

Abstract: An organic electroluminescent display includes a substrate having an array portion with pixels, and a pad portion coupled to an external power supply. A semiconductor structure is formed on the substrate with a source electrode, a drain electrode and a pad. A passivation layer is formed on the semiconductor structure with via holes exposing regions of the source and the drain electrodes at the array portion and the pad at the pad portion. Portions of the passivation layer contacting the via holes between the array portion and the pad portion have the same thickness. A conductive layer fills the via holes. A pixel defining layer is formed over the entire surface of a flattening layer and the conductive layer with pixel regions exposing regions of the conductive layer at the array portion. An organic electroluminescent film is formed at each pixel region.

Abstract: An integrated non-volatile memory circuit is formed by first growing a thin dielectric layer on a semiconductor substrate surface, followed by depositing a layer of conductive material such as doped polysilicon on this dielectric layer, the conductive material then being separated into rows and columns of individual floating gates. Cell source and drain diffusions in the substrate are continuously-elongated across the rows. Field dielectric deposited between the rows of floating gates provides electrical isolation between the rows. Shallow trenches may be included between rows without interrupting the conductivity of the diffusions along their lengths. A deep dielectric filled trench is formed in the substrate between the array and peripheral circuits as electrical isolation. Various techniques are included that increase the field coupling area between the floating gates and a control gate.

Abstract: It is an object to provide a liquid composition for forming a thin film, with which a ferroelectric thin film having excellent characteristics can be prepared even by baking at a low temperature, and a process for producing a ferroelectric thin film using it. The above object is achieved by use of a liquid composition for forming a ferroelectric thin film, characterized in that in a liquid medium, ferroelectric oxide particles being plate or needle crystals, which are represented by the formula ABO3 (wherein A is at least one member selected from the group consisting of Ba2+, Sr2+, Ca2+, Pb2+, La3+, K+ and Na+, and B is at least one member selected from the group consisting of Ti4+, Zr4+, Nb5+, Ta5+ and Fe3+) and have a Perovskite structure and which have an average primary particle size of at most 100 nm and an aspect ratio of at least 2, are dispersed, and a soluble metal compound which forms a ferroelectric oxide by heating, is dissolved.

Abstract: The present memory structure includes first and second electrodes, a passive layer, and an active layer containing nitrogen, the passive and active layers being between the first and second electrodes. Metal ions in the active layer bind to the nitrogen thereof, enhancing retention of the metal ions in the active layer for improved, stable data retention.