Abstract: In one aspect, a first region that includes a first Group IV semiconductor that has a bandgap and is doped with a first dopant of a first electrical conductivity type is formed. A pattern is created. The pattern controls formation of local crystal modifications in the first Group IV semiconductor in an array. An array of local crystal modifications is formed in the first Group IV semiconductor in accordance with the pattern. The local crystal modifications induce overlapping strain fields that increase the bandgap of the first Group IV semiconductor, create an energy band barrier against transport of minority carriers across the first region. A second region that includes a second Group IV semiconductor that has a bandgap and is doped with a second dopant of a second electrical conductivity type opposite the first conductivity type is formed. Semiconductor devices formed in accordance with this method also are described.

Abstract: A semiconductor memory device having a transistor formed on a semiconductor substrate and a capacitor formed on the upper layer of the transistor and electrically connected to the transistor, includes: a cell contact which is formed on a first interlayer insulation film covering the transistor and is electrically connected to the transistor; a bit contact which is formed on a second interlayer insulation film provided on the first interlayer insulation film and is electrically connected to the cell contact; a bit line which is formed on the second interlayer insulation film and is connected to the bit contact; a capacitor which is formed on a third interlayer insulation film covering the bit line; a capacitor contact which is formed through the third and second interlayer insulation film and makes a connection between the capacitor and the cell contact; and a side wall which has an etching selectivity with the second and third interlayer insulation films formed on the surface of the bit line.

Abstract: A method for fabricating semiconductor devices forms a semiconductor layer containing a positive layer on a mother substrate and then forms a metal layer on the semiconductor layer. After forming the metal layer, the method separates the mother substrate from the semiconductor layer and then removes a desired region of the metal layer from the exposed surface of the semiconductor layer from which the mother substrate has been separated to form a plurality of mutually separated semiconductor devices each containing the semiconductor layer.

Abstract: A semiconductor device mountable on a wiring board with the bottom surface being opposed to the wiring board including a semiconductor chip; a mold resin encapsulating the semiconductor chip; a first heat spreader joined to the semiconductor chip on the bottom surface side with both ends protruding from the mold resin, the first heat spreader being capable of being joined to the wiring board at both ends; and a second heat spreader joined to the semiconductor chip on a top surface side with both ends thereof protruding from the mold resin, the second heat spreader being capable of being joined to the wiring board at both ends. One of the heat spreaders is a lead frame electrically connected to the semiconductor chip. The first and second heat spreaders are substantially entirely covered with the mold resin on the bottom surface side and the top surface side, respectively.

Abstract: A method (100) of forming a transistor includes forming a gate structure (106, 108) over a semiconductor body and forming recesses (112) substantially aligned to the gate structure in the semiconductor body. Silicon germanium is then epitaxially grown (114) in the recesses, followed by forming sidewall spacers (118) over lateral edges of the gate structure. The method continues by implanting source and drain regions in the semiconductor body (120) after forming the sidewall spacers. The silicon germanium formed in the recesses resides close to the transistor channel and serves to provide a compressive stress to the channel, thereby facilitating improved carrier mobility in PMOS type transistor devices.

Abstract: A FinFET body contact structure and a method for creating the FinFET body contact structure are disclosed. The body contact structure comprises a wide fin portion of a semiconductor fin, the wide fin portion having a polysilicon polygon shape formed on a top surface of the wide fin portion. The polysilicon polygon shape has a center area having no polysilicon. FinFETs are formed on two vertical surfaces of the wide fin portion and gates of the FinFETs are coupled to the polysilicon polygon shape. Top surfaces of the wide fin portion and the polysilicon polygon shape are silicided. Silicide bridging is prevented by sidewall spacers. All convex angles on the polysilicon polygon shape are obtuse enough to prevent creation of bridging vertices. The center area is doped of an opposite type from a source and a drain of an associated FinFET.

Abstract: An integrated circuit that has logic and a static random access memory (SRAM) array has improved performance by treating the interlayer dielectric (ILD) differently for the SRAM array than for the logic. The N channel logic and SRAM transistors have ILDs with non-compressive stress, the P channel logic transistor ILD has compressive stress, and the P channel SRAM transistor at least has less compressive stress than the P channel logic transistor, i.e., the P channel SRAM transistors may be compressive but less so than the P channel logic transistors, may be relaxed, or may be tensile. It is beneficial for the integrated circuit for the P channel SRAM transistors to have a lower mobility than the P channel logic transistors. The P channel SRAM transistors having lower mobility results in better write performance; either better write time or write margin at lower power supply voltage.

Abstract: A semiconductor device of the present invention comprises a Group III-V nitride semiconductor layer of gallium nitride or the like having n-type conductivity and at least one ohmic electrode formed on the Group III-V nitride semiconductor layer of gallium nitride or the like having n-type conductivity. The ohmic electrode is formed of a conductive material containing a metal boride.

Abstract: A semiconductor device 100 comprises a silicon substrate 102, an N-type MOSFET 118 including a high concentration-high dielectric constant film 108b formed on the silicon substrate 102 and a polycrystalline silicon film 114, and a P-type MOSFET 120 including a low concentration-high dielectric constant film 108a and a polycrystalline silicon film 114 formed on the semiconductor substrate 102 to be juxtaposed to the N-type MOSFET 118. The low concentration-high dielectric constant film 108a and the high concentration-high dielectric constant film 108b are composed of a material containing one or more element (s) selected from a group consisting of Hf and Zr. The concentration of the above-described metallic element contained in the low concentration-high dielectric constant film 108a is lower than that contained in the high concentration-high dielectric constant film 108b.

Abstract: A method for forming a semiconductor device including a DRAM cell structure comprising a silicon on insulator (SOI) substrate with an embedded capacitor structure including providing a substrate comprising an overlying first electrically insulating layer; forming a first electrically conductive layer on the first electrically insulating layer to form a first electrode; forming a capacitor dielectric layer on the first electrode; forming a second electrically conductive layer on the capacitor dielectric layer to form a second electrode; forming a second electrically insulating layer on the second electrode; and, forming a monocrystalline silicon layer over the second electrode to form an SOI substrate comprising a first capacitor structure.

Abstract: The present invention provides an interconnect that can be employed in an integrated circuit. The interconnect includes a metal line located over a substrate, a dielectric layer located over the metal line, and an interconnect located in the dielectric layer, including a landed portion located over the metal line and an unlanded portion located along at least a portion of a lateral edge of the metal line. The unlanded portion is at least partially filled with a polymer, and the landed portion is substantially filled with a conductive material. A method for manufacturing the interconnect is also provided.

Abstract: A method of fabricating a semiconductor device. The method comprises creating a via in a dielectric layer that is formed on a substrate, filling the via, and optionally, the surface of the dielectric layer with a sacrificial material, patterning a first photoresist layer on the sacrificial material to define a trench for the semiconductor device, removing the first photoresist layer without affecting the sacrificial material, repatterning a second photoresist layer on the sacrificial material to define the trench for the semiconductor device, forming the trench, and removing the second photoresist layer and the sacrificial material completely after the trench is formed.

Abstract: A semiconductor junction varactor utilizes gate enhancement for enabling the varactor to achieve a high ratio of maximum capacitance to minimum capacitance.

Abstract: Disclosed are methods for facilitating concurrent formation of copper vias and memory element structures. The methods involve forming vias over metal lines and forming copper plugs, wherein the copper plugs comprise memory element film forming copper plugs (memE copper plugs) and non-memory element forming copper plugs (non-memE copper plugs), forming a tantalum-containing cap over an upper surface of non-memE copper plugs, and depositing memory element films. The tantalum-containing cap prevents the formation of the memory element films in the non-memE copper plugs. The subject invention advantageously facilitates cost-effective manufacturing of semiconductor devices.

Abstract: The average film thickness of an amorphous silicon film formed on a substrate is measured. Then, the amorphous silicon film is irradiated with a laser beam to form a polysilicon film, and the grain size distribution of the polysilicon film is measured. An optimum value of energy density of laser beam irradiation is calculated on the basis of grain size values measured at two points A and B of the polysilicon film. Then, the average film thickness of an amorphous silicon film formed on a subsequent substrate is measured. A value of energy density of laser beam irradiation for the subsequent amorphous silicon film is calculated on the basis of the two average film thicknesses. Accordingly, a uniform polysilicon film of large grain sizes is formed on the whole surface of a large-size substrate to provide polysilicon TFTs in a large area.

Abstract: A semiconductor substrate formed with a MOSFET is prepared, and a first interlayer insulating film is deposited on the semiconductor substrate. A ferroelectric capacitor is formed on the first interlayer insulating film. Next, a second interlayer insulating film is formed on a first structure provided with the semiconductor substrate, the first interlayer insulating film and the ferroelectric capacitor so as to embed the ferroelectric capacitor therein. Openings for electrically connecting the MOSFET and the ferroelectric capacitor and an external circuit of a ferroelectric memory are formed in the second interlayer insulating film to form a second structure. A metal wiring is formed on the second interlayer insulating film to form a third structure. Next, the third structure is heat-treated in an atmosphere from over 350° C. to under 450° C.

Abstract: A method and apparatus for an electronic substrate having a plurality of semiconductor devices is described. A thin film of nanowires is formed on a substrate. The thin film of nanowires is formed to have a sufficient density of nanowires to achieve an operational current level. A plurality of semiconductor regions are defined in the thin film of nanowires. Contacts are formed at the semiconductor device regions to thereby provide electrical connectivity to the plurality of semiconductor devices. Furthermore, various materials for fabricating nanowires, thin films including p-doped nanowires and n-doped nanowires, nanowire heterostructures, light emitting nanowire heterostructures, flow masks for positioning nanowires on substrates, nanowire spraying techniques for depositing nanowires, techniques for reducing or eliminating phonon scattering of electrons in nanowires, and techniques for reducing surface states in nanowires are described.

Abstract: This invention provides a new procedure for attaching molecules to semiconductor surfaces, in particular silicon. The molecules, which include, but are not limited to porphyrins and ferrocenes, have been previously shown to be attractive candidates for molecular-based information storage. The new attachment procedure is simple, can be completed in short times, requires minimal amounts of material, is compatible with diverse molecular functional groups, and in some instances affords unprecedented attachment motifs. These features greatly enhance the integration of the molecular materials into the processing steps that are needed to create hybrid molecular/semiconductor information storage devices.

Abstract: A first insulating film, a second insulating film, a third insulating film, an antireflective film, and a resist film are formed in this order on a lower-layer wiring. After dry etching the third insulating film and the second insulating film, using the resist film as a mask, the resist film and the antireflective film are removed by ashing. Thereafter, the first insulating film is dry etched, using the third insulating film as a mask, to form a wiring trench extending to the lower-layer wiring. The dry etching of the third insulating film and the second insulating film is performed using a gas containing fluorine at a pressure of 0.1 Pa to 4 Pa. Ashing is preferably performed using at least one of hydrogen and an inert gas.

Abstract: The MOS type solid-state imaging device has plural pixels each of which comprises a photo-diode and a MOS transistor on a substrate. A gate electrode is formed on the channel dope layer formed in the surface of the p-type well layer. By ion implantation of n-type impurity ions via the gate electrode as the mask, the n-type source region and the drain region are formed in the region corresponding to the MOS transistor, and the n-type impurity region is also formed in the region corresponding to the photo-diode. In the well layer, a high impurity density region as a hole pocket is self-aligned to the gate electrode.