Abstract: Disclosed are a phase-change random access memory device and a method for manufacturing the same. The phase-change random access memory includes a first insulation layer having first contact holes, conductive plugs for filling the first contact holes, a second insulation layer having a second contact hole, and a bit line. Third and fourth insulation layers and a nitride layer are sequentially formed on the second insulation layer and have third contact holes. Bottom electrodes are provided to fill the third contact holes. An opening is formed in order to expose a part of the third insulation layer and a cavity is connected with the opening so as to expose a part of the bottom electrode. A phase-change layer pattern is connected to one side of the bottom electrode. A top electrode is formed on the phase-change layer pattern.

Abstract: A process for manufacturing a phase change memory array, includes the steps of: forming a plurality of PCM cells, arranged in rows and columns; and forming a plurality of resistive bit lines for connecting PCM cells arranged on a same column, each resistive bit lines comprising a respective phase change material portion, covered by a respective barrier portion. After forming the resistive bit lines, electrical connection structures for the resistive bit lines are formed directly in contact with the barrier portions of the resistive bit lines.

Abstract: An opto-electronic device, such as an OLED or organic solar cell, having an electrode structure for use as a cathode. The electrode structure includes an electrically conductive layer and an inorganic layer, wherein the inorganic layer is made of at least one oxide-based alkali or alkaline earth metal intercalation compound. The intercalation compound having the chemical formula of Ax(MxOz), where x, y, z are positive integers greater than zero, A is an alkali metal or alkaline earth element, M is a metal, transitional metal or metallic alloy, and O is oxygen. Furthermore, a buffer layer made of alkali oxides or halides, or alkaline earth oxides or halides can be provided between the conductive layer and the inorganic layer.

Abstract: A top-emitting OLED display that includes a substrate; an array of OLED light emissive elements formed over the substrate; an encapsulating cover located over the OLED light emissive elements; and a circular light polarizer located between the encapsulating cover and the OLED light emissive elements. The present invention has the advantage that it improves the contrast and robustness of an OLED display by protecting the circular light polarizer from environmental wear and enables the application of additional structures on the top of the encapsulating cover.

Abstract: This integrated circuit comprises a capacitor (23) formed above a substrate (1) inside a first cavity in a dielectric and comprising a first electrode, a second electrode, a thin dielectric layer placed between the two electrodes, and a structure (7) for connection to the capacitor. The connection structure is formed at the same level as the capacitor in a second cavity narrower than the first cavity, the said second cavity being completely filled by an extension of at least one of the electrodes of the capacitor.

Abstract: Disclosed herein is a composition for forming an organic insulating film and an organic insulating film formed from the composition. An exemplary composition comprises an insulating polymer having a maleimide structure, a crosslinking agent and a photoacid generator so as to form a crosslinked structure. The organic insulating film has excellent chemical resistance to organic solvents used in a subsequent photolithographic process and can improve the electrical properties of transistors.

Abstract: A semiconductor device of the present invention includes capacitors made up of a lower electrode, a capacitive insulation film made from metal oxide material, provided on one surface of a semiconductor substrate. An ozone TEOS film is provided on these capacitors, and a protective film for covering the upper surfaces of the capacitors is then provided on this ozone TEOS film. An interlay insulation film that is thicker than the ozone TEOS film is provided on the protective film for covering the upper surfaces of the capacitors. In this way, the present invention prevents degradation in film quality of the capacitive insulation film due to mutual reaction etc. As a result, it becomes possible to provide a capacitor using an insulating film made of a metal oxide as a capacitive insulation film, having a protective film for sufficiently preventing diffusion of H2, a semiconductor device having high reliability, and a method of manufacturing such a semiconductor device, are provided.

Abstract: A method for assembling an electronic system with a plurality of layers. Recesses in formed in one or more dielectric layers and electronic components are positioned within the recesses. One or more layers containing the components are placed on a host substrate containing host circuits. Electrical interconnects are provided between and among the electronic components in the dielectric layers and the host circuits. The layers containing the components may also be provided by growing the electronic devices on a growth substrate. The growth substrate is then removed after the layer is attached to the host substrate.

Abstract: An electronic device having a semiconductor circuit formed therein includes a semiconductor device in which the semiconductor circuit is formed; and a light emitting device, formed integrally with the semiconductor device, for emitting light indicating a reference position of the semiconductor device.

Abstract: The semiconductor device comprises: a semiconductor substrate (N+ substrate 110) containing a first conductivity type impurity implanted therein; a second conductivity type impurity-implanted layer (P+ implanted layer 114) at relatively high concentration, formed on the semiconductor substrate (N+ substrate 110); a second conductivity type impurity epitaxial layer (P? epitaxial layer 111) at relatively low concentration, formed on the second conductivity type impurity-implanted layer (P+ implanted layer 114); and a field effect transistor 100 (N-channel type lateral MOSFET 100) composed of a pair of impurity diffusion regions (N+ source diffusion layer 115 and N? drain layer 116) provided in the second conductivity type impurity epitaxial layer (P? epitaxial layer 111) and a gate electrode 117 provided over a region sandwiched with the pair of impurity diffusion regions (N+ source diffusion layer 115 and N? drain layer 116).

Abstract: The invention includes methods of forming particle-containing materials, and also includes semiconductor constructions comprising particle-containing materials. One aspect of the invention includes a method in which a first monolayer is formed across at least a portion of a semiconductor substrate, particles are adhered to the first monolayer, and a second monolayer is formed over the particles. Another aspect of the invention includes a construction containing a semiconductor substrate and a particle-impregnated conductive material over at least a portion of the semiconductor substrate. The particle-impregnated conductive material can include tungsten-containing particles within a layer which includes tantalum or tungsten.

Abstract: A high ion energy and high pressure O2/CO-based plasma for ashing field photoresist material subsequent to via-level damascene processing. The optimized plasma ashing process is performed at greater than approximately 300 mT pressure and ion energy greater than approximately 500 W conditions with an oxygen partial pressure of greater than approximately 85%. The rapid ash rate of the high pressure/high ion energy process and minimal dissociation conditions (no “source” power is applied) allow minimal interaction between the interlevel dielectric and ash chemistry to achieve minimal overall sidewall modification of less than approximately 5 nm.

Abstract: A method for forming a temperature-compensated resistor on a semiconductor substrate is provided. A resistor element is formed on the semiconductor substrate. Terminal contacts are formed on the ends of the resistor element. A temperature-compensating configuration is formed, and is selected from an enlarged transverse portion in the resistor element intermediate and spaced from the terminal contacts, and at least one contact pattern along and in contact with the resistor element intermediate and spaced from the terminal contacts.

Abstract: The invention includes a method for selective deposition of semiconductor material. A substrate is placed within a reaction chamber. The substrate comprises a first surface and a second surface. The first and second surfaces are exposed to a semiconductor material precursor under conditions in which growth of semiconductor material from the precursor comprises a lag phase prior to a growth phase, and under which it takes longer for the growth phase to initiate on the second surface than on the first surface. The exposure of the first and second surfaces is conducted for a time sufficient for the growth phase to occur on the first surface, but not long enough for the growth phase to occur on the second surface.

Abstract: The present invention relates to an III-nitride semiconductor light emitting device in which a single layer or plural layers made of SixCyNz(x?0, y?0, x+y>0, z>0) are inserted into or under an active layer and it is directed to a technology in which Al(x)Ga(y)In(1?x?y)N(0?x?1, 0?y?1, 0?x+y?1) of the hexagonal structure and SixCyNz(x?0, y?0, x+y>0, z>0) of the hexagonal structure are combined together in view of the properties of the SixCyNz(x?0, y?0, x+y>0, z>0) material.

Abstract: In the case of the cost-effective method according to the invention for fabricating a power transistor arrangement, a trench power transistor arrangement (1) is fabricated with four patterning planes each containing a lithography step. The power transistor arrangement according to the invention has a cell array (3) with cell array trenches (5) each containing a field electrode structure (11) and a gate electrode structure (10). The field electrode structure (11) is electrically conductively connected to the source metallization (15) by a connection trench (6) in the cell array (3).

Abstract: A method for forming transistors with mutually-aligned double gates. The method includes the steps of (a) providing a wrap-around-gate transistor structure, wherein the wrap-around-gate transistor structure includes (i) semiconductor region, and (ii) a gate electrode region wrapping around the semiconductor region, wherein the gate electrode region is electrically insulated from the semiconductor region by a gate dielectric film; and (b) removing first and second portions of the wrap-around-gate transistor structure so as to form top and bottom gate electrodes from the gate electrode region, wherein the top and bottom gate electrodes are electrically disconnected from each other.

Abstract: A current-voltage response of at least one site of a semiconductor wafer where ions have been implanted in the semiconducting material of the semiconductor wafer is measured prior to annealing the semiconductor wafer. From the measured response, a determination is made whether the ion implantation is within acceptable tolerance(s).

Abstract: An IGBT includes a plurality of n+ doped regions (11) selectively formed in a main surface (103) of a p+ semiconductor layer (12) opposite from an n type semiconductor layer (80) without being connected to the n type semiconductor layer (80). The n+ doped regions (11) are formed in corresponding relation to and only under channel regions (CH1a-CH1d) of structures (200a-200d), respectively. This lowers the effective concentration of the p+ semiconductor layer (12) on the n+ doped regions (11) to reduce the number of holes injected from a collector layer (9) in an off state, reducing a leakage current.

Abstract: A method of processing a for an electronic device, comprising, at least: a nitridation step (a) of supplying nitrogen radicals on the surface of the electronic device substrate, to thereby form a nitride film on the surface thereof; and a hydrogenation step (b) of supplying hydrogen radicals to the surface of the electronic device substrate. By use of this method, it is possible to recover the degradation in the electric property of an insulating film due to a turnaround phenomenon which can occur at the time of nitriding an Si substrate, etc.