Abstract: The dummy oxide used to form DRAM capacitor cells is left in place over the peripheral transistors, reducing the height difference between the DRAM array and the peripheral circuitry and protecting against edge effects.

Abstract: A method for making improved MOSFET structures is achieved. A Si.sub.3 N.sub.4 and a SiO.sub.2 layer are deposited and patterned to have openings for gate electrodes over device areas on a substrate. A second Si.sub.3 N.sub.4 layer is deposited and etched back to form arc-shaped sidewall spacers in the openings. An anti-punchthrough implant and a gate oxide are formed in the openings between the Si.sub.3 N.sub.4 sidewall spacers. A polysilicon layer is deposited and polished back to form gate electrodes. The SiO.sub.2 and the Si.sub.3 N.sub.4 layers, including the sidewall spacers, are removed to form free-standing gate electrodes that increase in width with height, and having arc-shaped sidewalls. An implant through the edges of the arc-shaped gate electrodes results in lightly doped source/drains that are graded both in junction depth and dopant concentration to reduce hot electron effects. A second SiO.sub.

Abstract: A non-volatile memory has transistors and capacitors formed on a semiconductor substrate. The capacitors have a lower electrode, a ferroelectric film and an upper electrode stacked in order. An insulating film with at least one contact hole is formed on the substrate to cover the gate of each transistor. A side-wall insulating film is also formed to cover the side faces of the lower electrode and the ferroelectric film. A contact electrically connects the upper electrode and the source or drain of each transistor. The side-wall insulating film electrically isolates the contact from the lower electrode. The contact is made of a material at least the portion connected to the upper electrode and the other portion adjacent to that portion. The upper electrode is also made of that material. The upper electrode and the portion of the contact connected to the upper electrode are thus joined each other.

Abstract: A semiconductor device such as a light emitting semiconductor device comprising a mask layer having opening areas and a selective growing layer comprising a semiconductor grown selectively by way of the mask layer, with each of the mask layer and the selective growing layer being disposed by two or more layers alternately. The semiconductor device is manufactured by a step of laminating on a substrate a mask layer having opening areas and a selective growing layer comprising a semiconductor grown selectively way of a mask layer, each by two or more layers alternately and a subsequent step of laminating semiconductor layers thereon. Threading dislocations in the underlying layer are interrupted by the first mask layer and the second mask layer and do not propagate to the semiconductor layer. The density of the threading dislocations is lowered over the entire surface and the layer thickness can be reduced.

Abstract: A ferroelectric thin-film device comprises: a single crystal substrate; a conductive thin film formed on the single crystal substrate; and an oriented ferroelectric oxide thin film having a perovskite structure formed on the conductive thin film. The oriented ferroelectric thin film comprises a first layer having a composition changing from the interface with the conductive thin film in the thickness direction and a second layer having a constant composition formed on the first layer. The composition of the first layer and the composition of the second layer are substantially the same at the boundary between the first layer and the second layer.

Abstract: A gate electrode comprises a conductive gate electrode body and gate side walls. The channel region beneath the gate electrode has an NUDC structure having a p.sup.- impurity region and p.sup.+ impurity regions. The p.sup.- impurity region is formed before the gate electrode body. After the formation of the gate electrode body, the p.sup.+ impurity regions are formed by ion implantation before the gate side walls. The ion implantation is carried out perpendicular to the substrate so that the implanted ions will not reach further around the center of the channel region. Of the gate oxide films over the channel region, the thickness of the gate oxide films at both ends of the channel region is thinner than that of the gate oxide film in the middle of the channel length so as to suppress lowering of the current drivability.

Abstract: The present invention provides a method of forming trench capacitor with a sacrificial silicon nitride. A deep trench structure is formed in a substrate. A TEOS oxide layer is formed on the substrate and filled in said trench region, etched to a first level subsequently, wherein a portion of the TEOS oxide layer is remained in the trench region and a portion of the substrate exposed to form a trench sidewall. A thermally oxidation process is performed to form a collar oxide on the exposed substrate. A silicon nitride sidewall is formed on the collar oxide, then removing the residual TEOS oxide layer by wet etching. A bottom cell plate is formed in the lower trench region. The silicon nitride sidewall is removed. A dielectric film is formed along a surface of the bottom cell plate, the collar oxide, and the substrate, subsequently, a first conductive layer is formed on said dielectric film and refill in the trench region.