Abstract: A rope light includes a flexible lighting strip, multiple trapezoidal shaped flanges attached to the flexible lighting strip, and gaps evenly spaced between the flanges. The rope light may be attached to a wall or other surface by placing hooks or staples through the flanges or by placing hooks through slots in the flanges. The rope light may also be attached to a wall, or other surface, by using an attachment strip.

Abstract: A method of forming interconnections is provided. A defined metal layer is formed as a metal line on a provided substrate. An oxide layer is formed on the metal layer and on the substrate. A silicon nitride layer is formed on the oxide layer. The oxide layer and the silicon nitride layer constitute a seed layer. A via hole is formed in the silicon nitride layer to expose the oxide layer positioned over the metal layer. A dielectric layer is formed on the seed layer. Since the silicon nitride layer and the oxide layer are different, a part of the dielectric layer positioned on the silicon nitride layer is a silicon oxide layer having holes therein. The other dielectric layer positioned on the oxide layer within the via hole is a dense silicon oxide layer.

Abstract: A gate insulator layer is formed over the semiconductor substrate and a first silicon layer is then formed over the gate insulator layer. An anti-reflection layer is formed over the first silicon layer. A gate region is defined by removing a portion of the gate insulator layer of the first silicon layer and of the anti-reflection layer. A portion of the gate insulator layer is removed to have undercut spaces under the first silicon layer. A dielectric layer is then formed on the semiconductor substrate, on the sidewalls of the gate region, and within the undercut spaces. A spacer structure containing first type dopants is then formed on the sidewalls of the gate region. Following the removal of the anti-reflection layer, a second silicon layer containing second type dopants is formed over the semiconductor substrate and the first silicon layer.

Abstract: Method for forming an inter-level dielectric layer upon a substrate employed within a microelectronics fabrication. There is first provided a substrate. There is then formed upon the substrate a patterned microelectronics layer. There is then formed upon and between the patterned microelectronics layer and substrate a blanket first silicon oxide layer employing high density plasma chemical vapor deposition. There is then an optional exposure of the first blanket silicon oxide layer to a nitrogen plasma treatment prior to formation thereupon of a second blanket silicon oxide dielectric layer employing ozone assisted sub-atmospheric pressure thermal chemical vapor deposition, where the nitrogen plasma exposure results in improved gap fill within the silicon oxide dielectric layer, whereas avoidance of exposure to the nitrogen plasma results in formation of voids within the blanket second silicon oxide dielectric layer, leading to lower capacitance.

Abstract: A method for preventing tungsten contact plug loss problem after a backside pressure fault problem in a deposition chamber is provided. In the method, first deposited by a silane soak step and a tungsten nucleation layer is subsequently deposited, a heat treating step by a rapid thermal process is carried out at a temperature of at least 600° C. for a time period of at least 10 seconds. The heat treating step significantly improves the uniform distribution of the silicon prenucleation layer and substantially prevents the formation of any tungsten silicide layers such that during an etchback process, the dry etchant utilized does not remove a tungsten silicide layer at a much faster rate and thereby does not result in a plug loss problem.

Abstract: In a method of fabricating a semiconductor device having a MISFET of trench gate structure, a trench is formed from a major surface of a semiconductor layer of first conductivity type which serves as a drain region, in a depth direction of the semiconductor layer, a gate insulating film including a thermal oxide film and a deposited film is formed over the internal surface of the trench, and after a gate electrode has been formed in the trench, impurities are introduced into the semiconductor substrate of first conductivity type to form a semiconductor region of second conductivity type which serves as a channel forming region, and impurities are introduced into the semiconductor region of second conductivity type to form the semiconductor region of first conductivity type which serves as a source region.

Abstract: A method for making an integrated circuit capacitor includes forming an interconnection line adjacent a substrate, forming a first dielectric layer on the interconnection line, forming a first opening in the first dielectric layer, and forming a second opening in the interconnection line aligned with the first opening and having an enlarged width portion greater than a width of the first opening. The method further includes filling the first and second openings with a conductive metal to define a metal plug having a body portion and an anchor portion adjacent lower portions of the first dielectric layer. The method also includes forming a trench in the first dielectric layer adjacent the body portion of the metal plug, forming a first electrode lining the trench and contacting the metal plug, forming a second dielectric layer on the first electrode, and forming a second electrode on the second dielectric layer.

Abstract: A high Q inductor and its forming method is disclosed. In this forming method, a semiconductor substrate is first provided with a trench formed thereon. The trench is defined by dry etching and formed to a depth of 3˜5 &mgr;m. A material having a higher resistivity than that of the semiconductor is then provided to fill the trench. The material can be formed by first depositing an epitaxy layer with a lower dopant concentration than that of the semiconductor substrate by several orders of magnitude on the semiconductor substrate, then etching back the epitaxy layer to expose the surface of the semiconductor substrate. Thereafter, a dielectric layer is formed on the semiconductor substrate and the trench, and an inductor winding is formed on the dielectric layer above the trench to form the high Q inductor.

Abstract: The invention comprises methods of forming capacitors, methods of processing dielectric layers, and methods of forming a DRAM cell. In one implementation, a method of processing a dielectric layer comprises forming a high K oxygen containing dielectric layer over a substrate. The high K dielectric layer is annealed at a temperature of at least about 200.degree. C. and at a pressure of at least about 50 Torr in an ozone comprising atmosphere. In another implementation, annealing of the high K dielectric layer is conducted at a temperature of at least about 200.degree. C. and at a pressure of at least about 0.1 Torr in an ozone comprising atmosphere which is void of plasma. Pressures of greater than one atmosphere are most preferred. In another implementation, annealing of the high K capacitor dielectric layer is conducted at a substrate temperature of at least about 300.degree. C. in an activated oxygen atmosphere produced at least in part from oxygen subjected to remote microwave plasma.

Abstract: A semiconductor device includes a semiconductor substrate having a major surface, a source region of a second conductivity type, a drain region of the second conductivity type, and a first insulating layer formed over the major surface between the source region and the drain region. The device also includes a control electrode layer formed over the first insulating layer and a second insulating layer formed over the major surface. The device also includes a first wiring layer formed in the first contact hole and a second wiring layer formed in the second contact hole and connected to a pad and an internal circuitry, wherein the internal circuitry executes a predetermined operation and wherein the pad receives a signal from the internal circuitry or a signal from an external device.

Abstract: A dual voltage chip is fabricated with no intermediate-doped (LDD or MDD) area in the high-voltage transistors by adjusting the gate sidewall spacer thickness and the source/drain implant.

Abstract: A flash memory cell. A heavily doped region with the opposite polarity of the drain region is formed between the channel region and the drain region. The heavily doped region is in a bar shape extending towards both the drain and the source regions along a side of the floating gate. Furthermore, the reading operation is performed in reverse by applying a zero voltage to the drain region, and a non-zero voltage to the source region.

Abstract: An electrostatic discharge protective circuit under an input pad. The electrostatic discharge protective circuit has at least a MOS, wherein the MOS comprises a drain region, a gate structure and a source region. A metal silicon layer is on the gate structure and the source region, wherein the gate structure and the source region are coupled to each other through the metal silicon layer. A dielectric layer is over the drain region, the gate structure and the source region. A metal layer is over the dielectric layer. A via plug is in the dielectric layer, wherein the drain and the conductive layer are coupled to each other through the via plug. An input pad is over the MOS, wherein the metal layer is coupled to an input port and an internal circuit through the input pad.

Abstract: The invention provides an ESD protection circuit, which is formed on a semiconductor substrate. There is at least one MOS transistor branches out at a place between an I/O port and an internal circuit. The MOS transistor includes a drain region, a source region, a gate oxide layer, and a gate electrode. The source and the drain regions are formed in the substrate and located on each side of the gate electrode. An insulating layer is formed over the substrate to cover the MOS transistor. A drain contact is formed in the insulating layer with a contact to the drain region of the MOS transistor so that the drain region can be coupled to the internal circuit through the drain contact. A source contact is formed in the insulating layer with a contact to the source region of the MOS transistor so that the source region can be coupled to the I/O port through the source contact. Several floating silicide blocks is located between the insulating layer and the substrate at the drain region.

Abstract: A memory cell incorporating a chalcogenide element and a method of making same is disclosed. In the method, a doped silicon substrate is provided with two or more polysilicon plugs to form an array of diode memory cells. A layer of silicon nitride is disposed over the plugs. Using a poly-spacer process, small pores are formed in the silicon nitride to expose a portion of the polysilicon plugs. A chalcogenide material is disposed in the pores by depositing a layer of chalcogenide material on the silicon nitride layer and planarizing the chalcogenide layer to the silicon nitride layer using CMP. A layer of TiN is next deposited over the plugs, followed by a metallization layer. The TiN and metallization layers are then masked and etched to define memory cell areas.

Abstract: An improved method of fabricating a flash memory cell is disclosed. A tunnel oxide film is formed on active regions. A first conductive film and a protective film are sequentially formed on the tunnel oxide film. The protective film on the isolation film is selectively etched, thus forming a protective film pattern on the tunnel oxide film. A sacrificial conductive film is formed on the resultant structure. The sacrificial conductive film and the first conductive film pattern are over-etched until the sidewalls and the upper surface of the protective film pattern are exposed, thereby exposing the center of the isolation film and simultaneously forming a first conductive film pattern having sloped sidewalls. With the present invention, an electrical field is prevented from being concentrated in an area between a control gate electrode and a floating gate because the floating gate have a sloped sidewall profile instead of sharp edges.

Abstract: An exemplary implementation of the present invention includes a capacitor for a dynamic random access memory cell having a first plate; a second plate; and a dielectric layer interposed between said first and second plates, with the dielectric layer being dominated by electrode-limited conduction, which includes tantalum pentoxide and silicon nitride, or a combination of the two. In a preferred implementation, one of the two capacitor plates is formed from a silicon-germanium layer, the second plate is formed from a metal and the dielectric layer is formed from tantalum pentoxide.

Abstract: A semiconductor package includes a semiconductor package substrate having a frame type insulator which has a penetrating portion in a center portion of the substrate and a plurality of lead bars exposed to upper and lower surfaces of the insulator, a semiconductor chip on the semicondcutor package substrate, an upper surface of the semiconductor chip being attached to the lead bars, a plurality of pads on a center portion of an upper surface of the semiconductor chip, a plurality of wires respectively connecting the pads with an upper surface of the lead bars, and an upper cover protecting the wires, the pads and an upper surface of the semiconductor chip.

Abstract: A high density flash EEPROM provides increased nonvolatile storage capacity. A memory cell array includes densely packed memory cells, each cell having a semiconductor pillar providing shared source/drain regions for two vertical floating gate transistors that have individual floating and control gates distributed on opposing sides of the pillar. The control gates are formed together with interconnecting gate lines. First source/drain terminals are row addressable by interconnection lines disposed substantially orthogonal to the gate lines. Second source/drain terminals are column addressable by data lines disposed substantially parallel to the gate lines. Both bulk semiconductor and silicon-on-insulator embodiments are provided. If a floating gate transistor is used to store a single bit of data, an area of only 2F.sup.2 is needed per bit of data, where F is the minimum lithographic feature size. If multiple charge states (more than two) are used, an area of less than 2F.sup.2 is needed per bit of data.

Abstract: A novel vertical poly load device in 4T SRAM and a method for fabricating the same are disclosed. The poly load structure is a vertical device formed on a buried contact. The poly load vertical device is constructed by forming a hollow in a planarized dielectric layer with a high temperature oxide layer on the walls of the hollow and with lightly doped n-type polysilicon in the hollow. The poly load is connected to the respective drain of the driver transistor through the buried contact and to the gate of the respective gate of the other driver transistor through a connecting line. The resistance of the poly load will increase, as the voltage of the buried contact becomes low thereby reducing the standby current.