Abstract: A semiconductor device of the present invention includes a MISFET provided in an element formation region Re of a semiconductor substrate 11 and a trench isolation 13 surrounding the sides of the element formation region Re. An oxygen-passage-suppression film 23 is provided from the top of the trench isolation 13 to the top of a portion of the element formation region Re adjacent to the trench isolation 13. The oxygen-passage-suppression film 23 is made of a silicon nitride film or the like through which oxygen is less likely to permeate. Therefore, since it becomes hard that the upper edge of the element formation region Re of the semiconductor substrate 11 is oxidized, an expansion of the volume of the upper edge is suppressed, thereby reducing a stress.

Abstract: The present invention provides methods and apparatus related to preventing adhesive contamination of the electrical contacts of a semiconductor device in a stacked semiconductor device package. The methods and apparatus include providing a first semiconductor device with an adhesive flow control dam located on an upper surface thereof. The dam is positioned between electrical contacts and a substrate attach site on the upper surface of the first semiconductor device. The dam is rendered of a sufficient height and shape to block applied adhesive from flowing over the electrical contacts of the first semiconductor device when a second substrate is mounted onto the upper surface of the first semiconductor device. The semiconductor device package may be encapsulated with the dam in place or with the dam removed. The adhesive flow control dam thus protects the electrical contacts of the first semiconductor device from contamination by excess adhesive, which can result in unusable electrical contacts.

Abstract: A method of fabricating a thin film transistor for liquid crystal display is provided. A polysilicon island and a gate insulating layer covered on the polysilicon island are formed on a substrate. A metal layer is formed on the gate insulating layer. A pair of trenches exposing predetermined regions of the polysilicon island are formed in the metal layer and the gate insulating layer. P-type impurities are doped into the uncovered polysilicon regions of the polysilicon island. A gate electrode is formed by removing parts of the metal layer and the gate insulating layer. N-type impurities are doped into the exposed portions of the polysilicon island. Thereby LDD regions, and a source and a drain regions are formed at the regions doped with both n-type and p-type impurities and at the regions doped with only n-type impurities respectively.

Abstract: In a method of fabricating a semiconductor device having a MISFET of trench gate structure, a trench is formed from a major surface of a semiconductor layer of first conductivity type which serves as a drain region, in a depth direction of the semiconductor layer, a gate insulating film including a thermal oxide film and a deposited film is formed over the internal surface of the trench, and after a gate electrode has been formed in the trench, impurities are introduced into the semiconductor substrate of first conductivity type to form a semiconductor region of second conductivity type which serves as a channel forming region, and impurities are introduced into the semiconductor region of second conductivity type to form the semiconductor region of first conductivity type which serves as a source region.

Abstract: A method for tailoring properties of high k thin layer perovskite materials, and devices comprising such insulators are herein presented. The method comprise the steps of, first, substantially completing the manufacture of a device, which device contains the high k insulator in a polycrystalline form. The device, such as a capacitor, or an FET, went through the typically high temperature manufacturing process of a fabrication line. In the next step, the device is in situ ion implanted with such a dose and energy to convert a fraction of the polycrystalline material into an amorphous material state, hereby tailoring the properties of the insulator. The fraction of polycrystalline material converted to amorphous material might be 1. This process can be applied to many electronic devices and some optical devices. The process results in novel perovskite thin layer materials and novel devices fabricated with such materials.

Abstract: There is disclosed an apparatus for supporting singulated electronic devices during a testing operation, comprising: a main body and a support member, wherein said support member is made of non-conducting high-resistivity material and comprises a plurality of recesses, each said recess being adapted to receive an individual singulated device. There is also disclosed a method for testing such devices in which the devices are carried on support members through a testing process including one or more environmental control chambers.

Abstract: Salient electrodes on a semiconductor chip and leads on a film substrate are to be connected together with a high accuracy. A change in lead pitch which occurs at the time of connecting salient electrodes on a semiconductor chip and inner leads on a film substrate with each other is taken into account and a correction is made beforehand to the pitch of the inner leads. Likewise, a change in lead pitch which occurs at the time of connecting electrodes on a liquid crystal substrate and outer leads on the film substrate with each other is taken into account and a correction is made beforehand to the pitch of the outer leads.

Abstract: A high frequency bipolar transistor that has a silicon germanium intrinsic base region is formed in a semiconductor fabrication process that forms the extrinsic base regions after the intrinsic base region has been formed. The extrinsic base regions are epitaxially grown single crystal silicon that is doped during the growth.

Abstract: A rugged polysilicon electrode for a capacitor has high surface area enhancement with a thin layer by high nucleation density plus gas phase doping which also enhances grain shape and oxygen-free dielectric formation.

Abstract: In an optical semiconductor integrated circuit device in which a vertical pnp transistor and a photodiode are formed, the preferred embodiments of the present invention eliminates difficulty in performance improvement of the two elements. In an illustrative optical semiconductor integrated circuit device, a vertical pnp transistor and a photodiode have been formed, and first and second epitaxial layers and are stacked without doping. This enables a depletion layer forming region to be remarkably increased in the photodiode, and high-speed response becomes possible. Additionally, in the vertical pnp transistor, an n+ type diffusion region surrounds the transistor forming region. This can remarkably improve voltage endurance of the vertical pnp transistor 21.

Abstract: In an ion implantation method using an ion implantation equipment having an extraction electrode and a post accelerator, ion is uniformly implanted into a shallow region from the surface of a sample by setting an applied volt. of the post accelerator higher than an applied volt. of the extraction electrode.

Abstract: An exemplary embodiment relates to a method of using amorphous carbon in replacement gate integration processes. The method can include depositing an amorphous carbon layer above a substrate, patterning the amorphous carbon layer, depositing a dielectric layer over the patterned amorphous carbon layer, removing a portion of the deposited dielectric layer to expose a top of the patterned amorphous carbon layer, removing the patterned amorphous carbon layer leaving an aperture in the dielectric layer, and forming a metal gate in the aperture of the dielectric layer.

Abstract: A semiconductor device has a fuse to be blown with an energy beam. The semiconductor device has copper wiring levels formed on a semiconductor substrate on which semiconductor elements are formed, an uppermost wiring level formed on said copper wiring levels and including a refractory metal film connected to a top one of the copper wiring levels, the fuse formed from a part of the uppermost wiring level, and a surface protective film formed on the uppermost wiring level.

Abstract: A semiconductor device and method for fabricating the same which improves reliability of the semiconductor device is disclosed. The semiconductor device includes: a first insulating film and a gate electrode sequentially formed on a part of a semiconductor substrate; a first insulating spacer formed at both sides above the gate electrode; a second insulating spacer formed at both sides below the gate electrode; and a cobalt silicide film formed on a surface of the gate electrode at a predetermined depth.

Abstract: A Pt/Ti film is formed on a substrate, and the Pt/Ti film is patterned in to a bottom electrode. Subsequently, a SrTiO3film, that is, a dielectric film, is formed on the substrate by sputtering using a mixture of an Ar gas, an O2 gas and a N2 gas as a film forming gas. The SrTiO3 film is patterned into a capacitor dielectric film formed on the bottom electrode. A top electrode is then formed on the capacitor dielectric film. Since a N2 gas is used as the film forming gas in addition to an Ar/O2 gas, a SrTiO3 film with a high dielectric constant and small leakage can be formed at a low temperature. By using this SrTiO3 film, a thin film capacitor with high capacitance and good dielectric characteristics can be obtained.

Abstract: A metal gate complementary metal oxide semiconductor (CMOS) and a method of manufacturing the same is disclosed. The method includes depositing the metal gate electrode material as a final step before metallization of the device. Accordingly, the metal gate material is not subject to contamination during the fabrication process. The device is fabricated without the use of oxide spacers so that the finished device does not suffer from silicon faceting at the active silicon-to-shallow-trench-isolation-interface. Moreover, the dummy gate material is used to define planarization stops that allow precise planarization of the device during fabrication.

Abstract: A strong interface is formed between an interconnect and an encapsulating layer to prevent the lateral drift of material from the interconnect along the bottom of the encapsulating layer. Diffusion barrier material is deposited on the top surface of the interconnect using a selective deposition process. The diffusion barrier material may be epitaxially grown from the interconnect during the selective deposition of the diffusion barrier material on the top surface of the interconnect to promote adhesion of the diffusion barrier material to the interconnect. An encapsulating layer is deposited on top of the diffusion barrier material. The diffusion barrier material and the encapsulating layer are comprised of a similar chemical element to promote adhesion of the diffusion barrier material to the encapsulating layer. The diffusion barrier material on the top surface of the interconnect prevents lateral drift of material comprising the interconnect along the encapsulating layer.

Abstract: A method for forming a capacitor by stacking impurity-doped polysilicon layers having different concentrations to form a bottom electrode, treating surfaces of the bottom electrode to prevent a low dielectric constant material from being generated on the surface of the bottom electrode, and forming a dielectric layer and a top electrode on the bottom electrode.

Abstract: A method of forming a co-axial interconnect line in a dielectric layer is provided. The method includes defining a trench in the dielectric layer and then forming a shield metallization layer within the trench. After forming the shield metallization layer, a conformal oxide layer is deposited within the shield metallization layer. A center conductor is then formed within the conformal oxide layer. Once the center conductor is formed, a fill oxide layer is deposited over the center conductor. A cap metallization layer is then formed over the fill oxide layer and is in contact with the shield metallization layer.

Abstract: A material layer which contains nitrogen atoms is formed on a first wiring or at a side surface of a first wiring. When etching for forming a via hole is carried out, nitrogen atoms contained in the material layer bind with CF molecules, CF2 molecules, CF3 molecules and the like contained in an etching gas, and compounds thus formed adhere to a surface of a silicon dioxide layer at side walls and a bottom portion of a via hole. As a result, once the material layer is exposed during etching for forming a hole, thereafter, the etching rate decreases. Accordingly even if there is misalignment of a via hole pattern with respect to a first wiring pattern when the via hole pattern is formed by lithography, etching of the silicon dioxide layer does not proceed to an underlying silicon substrate. Thus, short circuits are not formed between the first wiring and the silicon substrate via a second wiring layer which is deposited later.