Abstract: This invention provides a method of forming a CMOS image sensor. The image sensor is formed in a predetermined region of a semiconductor wafer covered with a P-type substrate. The wafer comprises at least one N-channel area for forming one NMOS transistor and a sensor area for forming a photo-diode sensor. At least one gate electrode in the N-channel area is formed first. A first ion-implantation is performed to form a lightly doped drain (LDD) layer in predetermined areas on the surface of the P-type substrate in the N-channel area next to the gate electrode. A second ion-implantation is performed to form a heavy doped drain (HDD) layer in another predetermined area on the surface of the substrate in the N-channel area next to the LDD. A third ion-implantation is performed to form a doped layer with phosphorus as the major dopant on the surface of the substrate in the sensor area.

Abstract: A method for removing a resistive film formed on an electrode to increase the conductive contact area of the electrode positioned in a misaligned contact hole. The method comprises providing a substrate supporting an electrode layer. The electrode layer is etched to produce metal lines. During the processing of the metal lines, a resistive film is formed thereon. The resistive film is removed and a protective barrier is formed on the metal lines. A dielectric layer is formed on the substrate, including the metal lines. The dielectric layer is subsequently patterned to form contact holes or vias to expose a portion of the metal lines. The contact holes are filled with plugs such that a second electrode layer can be formed on the dielectric layer and the plugs.

Abstract: A method for making an integrated circuit capacitor which in one embodiment preferably comprises the steps of: forming, adjacent a semiconductor substrate, a first metal electrode comprising a metal nitride surface portion; forming a tantalum pentoxide layer on the metal nitride surface portion while maintaining a temperature below an oxidizing temperature of the metal; remote plasma annealing the tantalum pentoxide layer; and forming a second electrode adjacent the tantalum pentoxide layer. The step of forming the tantalum pentoxide layer preferably comprises chemical vapor deposition of the tantalum pentoxide at a temperature below about 500° C. Accordingly, oxidation of the metal is avoided and a high quality tantalum pentoxide is produced. The metal of the first metal electrode may comprise at least one of titanium, tungsten, tantalum, and alloys thereof.

Abstract: A semiconductor p-i-n photodiode having a substrate, an n layer coupled to the surface of said substrate, an i layer coupled to the surface of said n layer, and a carbon doped p layer coupled to the surface of said i layer.

Abstract: A method and an apparatus for forming a plastic chip on chip module is disclosed. The plastic chip on chip module is formed by placing a stacked chip set into a molding chamber suitably arranged to receive encapsulant. The stacked chip set includes a daughter chip that is electrically and mechanically coupled to a mother chip where the daughter chip is directly aligned to and separated from the mother chip by a standoff gap. Encapsulant is then passed into the molding chamber filling the standoff gap substantially simultaneously with surrounding the chip set to form the plastic chip on chip module.

Abstract: The present invention provides a method of forming a gate recess in an insulating film on a substrate for depositing a gate electrode film being in contact with a part of the substrate and also extending at least within the gate recess.

Abstract: A method for fabricating a ferroelectric memory device, comprising the steps of: providing a semiconductor substrate where a transistor having an impurity region is formed; forming a conduction layer for storage node over the substrate; forming a ferroelectric film on the conduction layer; patterning the conduction layer and the ferroelectric film to form a storage node and a dielectric film; forming a protection film for dielectric film over the semiconductor substrate to cover the storage node and the dielectric film; patterning the protection film to expose a selected portion of the dielectric film; and forming a plate node on the dielectric film.

Abstract: Borderless vias are formed by depositing a hard dielectric mask layer on the upper surface of a lower metal feature and forming sidewall spacers on the side surfaces of the metal feature and mask layer. A dielectric interlayer is deposited and a misaligned through-hole formed therein by etching. The dielectric material of the sidewall spacer and dielectric material of the dielectric interlayer are different. The etchant employed to form the through-hole exhibits a high selectivity with respect to the sidewall spacer material. The dielectric mask layer enables the formation of a sidewall spacer extending above the metal feature such that, after etching to form the misaligned through-hole, the sidewall spacer covers the side surface of the metal feature.

Abstract: A circuit module includes at least one high temperature semiconductor chip having chip pads; a substrate having substrate metallization, the chip pads and the substrate metallization being substantially planar; and a deposited flexible pattern of electrical conductors capable of withstanding high temperatures and coupling selected chip pads and portions of the substrate metallization. The deposited flexible pattern of electrical conductors includes a plurality of integral interconnect segments, at least one of the integral interconnect segments including first and second leg portions and a shelf portion with the shelf portion being spaced apart from the at least one semiconductor chip and substrate and being coupled by the first leg portion to a selected chip pad and by the second leg portion to a selected portion of the substrate metallization.

Abstract: A memory cell which comprises a substrate having a top surface; a capacitor extending vertically into the substrate for storing a voltage representing a datum, said capacitor occupying a geometrically shaped horizontal area; a transistor formed above the capacitor and occupying a horizontal area substantially equal to the geometrically shaped horizontal area, and having a vertical device depth, for establishing an electrical connection with the capacitor, in response to a control signal, for reading from, and writing to, the capacitor, wherein the transistor includes a gate formed near the periphery of said horizontal device area and having a vertical depth approximately equal to the vertical device depth; an oxide layer on an inside surface of the gate; a conductive body formed inside the oxide layer, said conductive body having a top surface and a bottom surface and a vertical depth approximately equal to the vertical device depth; and diffusion regions in the body near the top and bottom surfaces and a met

Abstract: A MOS type semiconductor apparatus is provided which includes a main MOS type semiconductor device, an internal control circuit connected between a control input terminal (G) and a control input port (g) of the main MOS type semiconductor device, and a protecting device connected between the control input terminal (G) and one of output terminals (S) of the apparatus, for protecting the semiconductor device or internal control circuit against overvoltage. The protecting device includes a first branch including a Zener diode (Z1p) consisting of a polysilicon layer deposited on an insulating film over the semiconductor substrate, and a second branch including a Zener diode (Z21) formed in a surface layer of the semiconductor substrate, and a diode (Z3pr) that consists of a polysilicon layer deposited on an insulating film over the semiconductor substrate, and is connected in series with the Zener diode (Z21) in a reverse direction. The first and second branches are connected in parallel with each other.

Abstract: A technique for forming an integrated circuit device having a self-aligned gate layer. The method includes a variety of steps such as providing a substrate, which is commonly a silicon wafer. Field isolation regions including a first isolation region and a second isolation region are defined in the semiconductor substrate. A recessed region is defined between the first and second trench isolation regions. The isolation regions are made using a reactive ion etching technique. A thickness of material such as polysilicon is deposited overlying or on the first isolation region, the second isolation region, and the active region. A step of selectively removing portions of the thickness of material overlying portions of the first isolation region and the second isolation region is performed, where the removing step forms a substantially planar material region in the recessed region. The substantially planar material region is self-aligned into the recessed region using the removing step.

Abstract: A solderable light-emitting diode (LED) chip and a method of fabricating an LED lamp embodying the LED chip utilize a diffusion barrier that appreciably blocks molecular migration between two different layers of the LED chip during high temperature processes. In the preferred embodiment, the two different layers of the LED chip are a back reflector and a solder layer. The prevention of intermixing of the materials in the back reflector and the solder layer impedes degradation of the back reflector with respect to its ability to reflect light emitted by the LED. The LED chip includes a high power AlInGaP LED or other type of LED, a back reflector, a diffusion barrier and a solder layer. Preferably, the back reflector is composed of silver (Ag) or Ag alloy and the solder layer is made of indium (In), lead (Pb), gold (Au), tin (Sn), or their alloy and eutectics. In a first embodiment, the diffusion layer is made of nickel (Ni) or nickel-vanadium (NiV).

Abstract: For providing a semiconductor package with improved moisture resistance and high reliability and a production method thereof, a solder resist is also provided in an appropriate thickness between electrodes of conductor circuits on a surface of a substrate. The resist in these portions is obtained by patterning the solder resist while leaving the solder resist between the conductor circuits by removing the unnecessary solder resist under irradiation of a laser.

Abstract: A method for attaching bumped semiconductor dice to substrates, such as printed circuit boards and multi chip modules, is provided. The method includes the steps of: providing an instant curing adhesive formulated to cure within 0.25 to 60 seconds, and dispensing a volume of the adhesive onto the substrate. The method also includes the steps of heating the die, and aligning the contact bumps on the die to the contacts on the substrate. Following these steps the die can be brought into contact with the substrate to form an adhesive layer therebetween. Heat from the die cures the adhesive layer. In addition, the cured adhesive layer tensions the die against the substrate, and compresses the contact bumps and contacts to form low resistance electrical connections. A system for performing the method includes a lead-on-chip die attacher configured to heat the die, to dispense the adhesive, to align the die and substrate, and then to press the die against the substrate with a desired pressure.

Abstract: A method of forming a conformal aluminum film on a refractory metal nitride layer is provided and includes positioning a substrate having the refractory metal nitride layer thereon within a chemical vapor deposition chamber; establishing a nominal temperature for the substrate; introducing a carrier gas containing a gaseous, metalorganic precursor into the chamber for a time sufficient to form a metallic seed layer; and introducing a carrier gas containing a gaseous aluminum metalorganic precursor into the chamber for a time sufficient to form a conformal aluminum metal film over the metal refractory nitride layer.

Abstract: A semiconductor memory device and a fabricating method therefor are disclosed. The semiconductor memory device includes a peripheral region and a core region containing a transistor with at least a p+ impurity region. An inter-layer insulating layer is formed on an entire surface of a semiconductor substrate. Then the insulating layer is etched by using a contact forming mask until the surface of the p+ impurity region of the core region is exposed, so as to form contact holes. The contact holes are then filled with a metal to form contacts so as to be electrically connected to the semiconductor substrate. The present invention solves the conventional problem that the contact plug reacts with the impurity ions of the p+ impurity region during the heat treatment, thereby increasing the contact resistance.

Abstract: The present invention provides a method for fabricating a trench capacitor, in particular for use in a semiconductor memory cell (100), with an insulation collar (168′; 168″), having the following steps: provision of a substrate (101); formation of a trench (108) in the substrate (101); provision of a first layer (177) on the trench wall; provision of a second layer (178) on the first layer (177) on the trench wall; filling of the trench (108) with a first filling material (152); removal of the first filling material (152) from the upper region of the trench (108) in order to define a collar region; removal of the second layer (178) from the upper region of the trench (108); removal of the first filling material (152) from the lower region of the trench (108); removal of the first layer (177) from the upper region of the trench (108); local oxidation of the upper region of the trench (108) in order to produce the insulation collar (168′; 168″); removal of the first and second layers (1

Abstract: A microelectronic connection component includes a support such as a dielectric sheet having elongated leads extending along a surface. The leads have terminal ends permanently connected to the support and tip ends releasably connected to the support. The support is juxtaposed with a further element such as a semiconductor chip or wafer, and tip ends of the leads are bonded to contacts on the wafer using a bonding tool advanced through holes in the support. After bonding, the support and the further element are moved away from one another so as to deform the leads.

Abstract: A stacked semiconductor package with ultrahigh integration and a fabrication method thereof according to the present invention are provided to meet the requirements of a system device of being miniaturized and light-weighted and having high efficiency. Also, there is provide a jig for package aligning to fabricate the stacked semiconductor package. The semiconductor package according to the present invention is fabricated by mounting a second-type package including a molding portion and leads exposed at a lower surface of the molding portion of the second-type package on a first-type package including a molding portion and leads, each of being formed in a ‘J’ shape, which are respectively extended out of both sides of the molding portion. Here, uppermost surfaces of the leads of the first-type package are welded by solder to bottom surfaces of the leads of the second-type package.