Abstract: In an apparatus for growing a semiconductor single crystal from semiconductor melt, a crucible retains the semiconductor melt. An electrode contacts with the semiconductor melt and applies current to the semiconductor melt. The electrode is formed of the same material as the semiconductor crystal.

Abstract: An apparatus and method of planarizing objects, particularly electronic components. The off-concentric polishing system of the present invention comprises at least two polishing platens positioned adjacent each other such that the polishing portions of the platens are substantially co-planar. At least one wafer carrier is moveably mounted over the at least two platens such that a wafer may be polished by more than one platen substantially simultaneously. The platen configurations may be in a linear or non-linear configuration such that the wafer being polished is no longer centrally disposed over a single platen but is off-concentrically positioned over multiple platens. The off-concentric positioning of the wafer provides enhanced slurry distribution and endpoint detection. The present invention reduces time and cost in manufacturing electronic components by engaging several polishing conditions simultaneously without the need for sequential polishing.

Abstract: To provide a semiconductor device production method capable of solving the problem of the latent period of time in which polishing is hardly performed immediately after a polishing start. In order to reduce the latent period of time caused immediately after a metal film polishing start, the polishing process is preceded by an oxide removal step for removing oxide from an object to be polished.

Abstract: In the semiconductor wafer manufacturing method of the present invention, a deteriorated layer on the surface of a semiconductor wafer which has been made flat by lapping or polishing is removed by the following dry etching. Plasma which contains a neutral active species is generated within a discharge tube. The neutral active species is separated from the plasma thus generated and is then conveyed to an orifice side of a nozzle portion of the discharge tube. The orifice is opposed to the wafer surface and the nozzle portion moves along the wafer surface while the neutral active species is sprayed from the nozzle orifice toward the wafer surface which is pre-heated. By such dry etching, the deteriorated layer on the wafer surface is removed without the occurrence of any etch pit.

Abstract: A gas distribution system for uniformly or non-uniformly distributing gas across the surface of a semiconductor substrate. The gas distribution system includes a support plate and a showerhead which are secured together to define a gas distribution chamber therebetween. A baffle assembly including one or more baffle plates is located within the gas distribution chamber. The baffle arrangement includes a first gas supply supplying process gas to a central portion of the baffle chamber and a second gas supply supplying a second process gas to a peripheral region of the baffle chamber. Because the pressure of the gas is greater at locations closer to the outlets of the first and second gas supplies, the gas pressure at the backside of the showerhead can be made more uniform than in the case with a single gas supply.

Abstract: A method and an apparatus for determining end point in a chemical mechanical polishing process by utilizing two separate laser beams are provided. When two separate laser beams of different wavelengths are utilized, the difference in the wavelengths is at least about 50 nm. For instance, one wavelength may be about 633 nm, while the other wavelength may be about 700˜950 nm. When two laser beams of different incident angles are utilized, the difference in the angles may be at least 2°, and preferably at least 5°.

Abstract: Improved CMP uniformity is achieved by providing improved control of the slurry distribution. Improved slurry distribution is achieved by, for example, the use of a slurry dispenser that dispenses slurry from a plurality of dispensing points. Providing a squeeze bar between the slurry dispenser and wafer to redistribute the slurry also improves the slurry distribution.

Abstract: A solid state thermal switch providing thermal conductivity in an ON state and enhanced thermal isolation in an OFF state. The thermal switch is manufactured on a substrate by forming an oxide layer under a thin semiconducting layer. The thin semiconducting layer can be made from silicon or a silicon geranium lattice structure. The thin silicon layer is cracked by a neutron bombardment process. A drain and a source are then doped into the thin silicon layer. Cracks in the thin silicon layer disrupt quiescent thermal conductivity in the electron transport layer between the drain and source when the solid state thermal switch is in the OFF state. The thin semiconducting layer transports electrons and heat when the solid state thermal switch is in the ON state. The cracks created in the silicon layer provide thermal isolation from the drain to the source when the thermal switch is in an OFF state and allow heat conduction when the solid state thermal device is in the ON state.

Abstract: A polishing composition comprising the following components: (a) an abrasive, (b) &agr;-alanine, (c) hydrogen peroxide, and (d) water.

Abstract: A combination CMP-etch method for forming a thin planar layer over the surface of a device includes the steps of providing a substrate including a plurality of surface projections defining gaps therebetween, forming an etchable layer on the substrate, performing a CMP process on the etchable layer to form a planar layer having a first thickness in excess of 1,000 Angstroms, and etching the planar layer to a second thickness less than 1,000 Angstroms. In a particular method, the step of forming the etchable layer includes the steps of forming an etch resistant layer on the substrate, forming a fill layer on the etch-resistant layer, etching the fill layer to expose portions of the etch-resistant layer overlying the projections, and to leave a portion of the fill layer in the gaps, and forming the etchable layer on the exposed portions of the etch-resistant layer and the fill layer.

Abstract: The semiconductor wafer includes a substrate, a gate positioned on the substrate, a cap layer positioned on top of the gate, and a silicon oxide spacer positioned around both the gate and the cap layer. Firstly, a dielectric layer is formed on the semiconductor wafer to cover the gate. An etching back process is then performed to remove portions of both the dielectric layer and the silicon oxide spacer. Finally, a silicon nitride spacer is formed on the dielectric layer around the cap layer. The silicon nitride spacer is positioned on the surface of the dielectric layer and functions in reducing stress between the silicon nitride spacer and the substrate.

Abstract: A method for removing a portion of an upper layer of one material from an underlying layer of another material to form a uniformly planar surface on a semiconductor wafer. In accordance with one embodiment of the invention, an upper section of the upper layer is etched to an intermediate point in the upper layer. The etching step removes the upper section of the upper layer and leaves only a lower section of the upper layer on the wafer. The lower section of the upper layer is then planarized to a final endpoint. The etching step preferably moves the majority of the upper layer from the wafer so that the remaining portion of the upper layer is thick enough to allow the planarization step to produce a uniformly planar finished surface on the wafer.

Abstract: An etchant for copper or copper alloys comprising 5-50 wt % of an alkanolamine, a copper ion source in the amount of 0.2-10 wt % as copper, a halide ion source in the amount of 0.005-10 wt % as halogen, 0.1-30 wt % of an aliphatic carboxylic acid, and the balance water, wherein the molar ratio of the alkanolamine to one mol of the aliphatic carboxylic acid is two or more. The etchant is free from problems such as instability of the liquid composition and unpleasant odor, has a high etching rate, exhibits only very slight corrosion even if a small amount of residue is left on the surface and is capable of producing a roughened surface when used for microetching.

Abstract: The copper-based metal polishing composition causes Cu or Cu alloy not to be dissolved at all in immersing Cu or Cu alloy therein, and makes it possible to polish Cu or Cu alloy at a high rate in polishing treatment. Such a copper-based metal polishing composition comprises a water-soluble first organic acid capable of reaction with copper to produce a copper complex compound which is substantially insoluble in water and has a mechanical strength lower than that of copper, at least one second organic acid selected from an organic acid having a single carboxyl group and a single hydroxyl group and oxalic acid, an abrasive grain, an oxidizing agent, and water.

Abstract: A plasma processing apparatus having a vacuum vessel and a supporting means for supporting a processing target in the vacuum vessel, the apparatus comprising means for introducing a gas into a plasma generating space, means for feeding electric energy to the gas in the plasma generating space to generate a plasma, a metal member for forming negative ions which is provided on the downstream side of the plasma generating space in such a way that it comes into contact with particles of the plasma, and means for feeding the negative ions to the processing target. Utilizing the electric charge exchange reaction between plasma particles and metal surfaces, negative ions can be formed continuously and in a high density and also the negative ions can be made incident on a processing target to make ashing, etching or cleaning of the processing target to remove unwanted matter therefrom, so that a high processing rate and less charge-up damage can be achieved.

Abstract: An apparatus for forming a portion of an electronic device is described incorporating an Ultra High Vacuum-Chemical Vapor Deposition (UHV-CVD) system, a Low Pressure-Chemical Vapor Deposition (LP-CVD) system, and an Ultra High Vacuum (UHV) transfer system. A method for passivating a semiconductor substrate is described incorporating growing silicon containing layers, flowing a hydrogen containing gas and lowering the substrate temperature below 400° C. A method for removing native oxide is described. A method for growing a continuous epitaxial layer while performing a deposition interrupt is described. A method for forming a Si/Si oxide interface is described having low interface trap density. A method for forming a Si/Si oxide/p++ polysilicon gate stack. The invention overcomes the problem of requiring silicon containing wafers being dipped in HF acid prior to CVD processing. The invention overcomes the problem of surface passivation between in-situ processes in multiple CVD reactors.

Abstract: A wafer having a substrate and an insulating layer over the substrate that includes a conductive layer over the insulating layer. The conductive layer mitigates charges formed on a photoresist layer during etching of features (e.g., vias and trenches). Any conductive material may serve this purpose. For example, aluminum, tantalum nitride, titanium and titanium nitride. Typically, a plasma etcher is employed for forming vias and trenches in an insulating layer to create contacts and conducting lines used to connect devices residing within different layers. The plasma etcher causes charge buildup on a photoresist layer that is utilized during the etching process. The charge buildup causes potential differences on the photoresist layer, which can lead to eventual damage of devices. A conductive layer eliminates this potential differences because a charge equilibrium is established due to the conductivity of the conductive layer.

Abstract: A substrate is provided. A first dielectric is formed over the substrate, and an etching stop layer and a second dielectric are formed in turn on the first dielectric by deposition. An anti-reflection layer is formed over the second dielectric. Then, a photo-resist layer is formed and defined over the anti-reflection layer. A gap-filling material is filled on the second dielectric and into the via hole. Subsequently, the gap-filling material is etched back and is turned on the end point and the long over etch is applied to make sure the photo-resist thickness is below middle stop layer. If the first dielectric reacts with the photo-resist plug in the via hole, the bottom anti-reflection coating or thin oxide are used as a barrier before the trench photo-resist is patterned. If the first dielectric does not react with the photo-resist plug in the via hole, the trench photo-resist is patterned directly. Then, the trench etch is performed.

Abstract: A method for planarizing an oxide surface and removing dishing or erosion defect from a semiconductor wafer. An apparatus for carrying out the planarization process on a semiconductor wafer is further described. In the method, a wafer that has metal residues or dishing or erosion defect after a copper CMP process is first rotated at a rotational speed of at least 1000 RPM, while simultaneously a solvent/abrasive particles mixture is injected onto the rotating surface for a sufficient length of time until the metal residues, the dishing or erosion defect is removed. The rotational speed of the semiconductor wafer can be suitably controlled in a range between about 1000 RPM and about 10,000 RPM. For the removal of an oxide layer, a suitable solvent of diluted HF and a suitable abrasive particle such as aluminum oxide may be used.

Abstract: A dual damascene process includes the steps of forming a contact hole in an oxide layer disposed above a semiconductor substrate, disposing a layer of anti-reflective coating material on top of the oxide layer and in the contact hole, and partially etching the layer of anti-reflective coating material and the oxide layer to form the wiring trough. The partial etching step includes the steps of spin coating photoresist on top of the anti-reflective coating material, exposing the photoresist through a mask containing a pattern of the wiring trough, developing the photoresist to expose portions of the anti-reflective coating material, dry etching the exposed portions of the anti-reflective coating material to expose portions of the oxide layer, and wet etching the exposed portions of the oxide layer to form the wiring trough.