Abstract: In a method for manufacturing a semiconductor device, a first conductive layer is formed on a semiconductor substrate. Then, a plasma etching process using Ar ions is performed upon the first conductive layer to remove natural oxide from the first conductive layer. Then, a heating process at a temperature higher than about 650° C. is performed upon the first conductive layer to expel Ar atoms from the first conductive layer. Finally, a second conductive layer is formed by a sputtering process on the first conductive layer.

Abstract: Disclosed is a process for removing doped silicon dioxide from a structure selectively to undoped silicon dioxide. A structure having both doped and undoped silicon dioxide regions is exposed to a high density plasma etch having a fluorinated etch chemistry. Doped silicon dioxide is preferably removed thereby at a rate 10 times or more greater than that of undoped silicon dioxide. The etch is conducted in a chamber having an upper electrode to which a source power is applied and a lower electrode to which a bias power is applied sufficient to generate a power density on a surface of the structure such that the source power density is in a range less than or equal to about 1000 W per 200-mm diameter wafer surface. The high density plasma etch has an ion density not less that about 109 ions/cm3. A variety of structures are formed with the etch process, including self-aligned contacts to a semiconductor substrate.

Abstract: A resist removing composition comprising a quaternary ammonium hydroxide, a water-soluble amine, an alkylpyrrolidone and a sugar or sugar alcohol. The photoresist removing composition can easily remove (i) a photoresist layer applied onto an inorganic substrate, (ii) a remaining photoresist layer after dry etching or (iii) a photoresist residue after ashing, at a low temperature in a short time, and also enables hyperfine processing of a wiring pattern material to manufacture a high precision circuit pattern without corroding the material.

Abstract: A method for forming a patterned oxygen containing plasma etchable layer. There is first provided a substrate. There is then formed upon the substrate a blanket oxygen containing plasma etchable layer. There is then formed upon the blanket oxygen containing plasma etchable layer a blanket hard mask layer. There is then formed upon the blanket hard mask layer a patterned photoresist layer. There is then etched while employing a first plasma etch method in conjunction with the patterned photoresist layer as a first etch mask layer the blanket hard mask layer to form a patterned hard mask layer. There is then etched while employing a second plasma etch method in conjunction with at least the patterned hard mask layer as a second etch mask layer the blanket oxygen containing plasma etchable layer to form a patterned oxygen containing plasma etchable layer.

Abstract: A laminate article comprises a substrate and a biaxially textured (RE1xRE2(1−x))2O3 buffer layer over the substrate, wherein 0<x<1 and RE1 and RE2 are each selected from the group consisting of Nd, Sm, Eu, Ho, Er, Lu, Gd, Tb, Dy, Tm, and Yb. The (RE1xRE2(1−x))2O3 buffer layer can be deposited using sol-gel or metal-organic decomposition. The laminate article can include a layer of YBCO over the (RE1xRE2(1−x))2O3 buffer layer. A layer of CeO2 between the YBCO layer and the (RE1xRE2(1−x))2O3 buffer can also be include. Further included can be a layer of YSZ between the CeO2 layer and the (RE1xRE2(1−x))2O3 buffer layer. The substrate can be a biaxially textured metal, such as nickel. A method of forming the laminate article is also disclosed.

Abstract: In an improved method for etching a groove n the uppermost layer of a semiconductor wafer, a conventional anisotropic etch is performed to achieve a narrow groove and an isotropic etch is performed to widen the groove at the device surface and thereby round the edges where the walls of the groove meet the surface of the wafer. During a later step of applying a protective tape to the device side of the wafer to protect it during a step of grinding the back of the wafer, the rounded edges of the groove are unlikely to cut through the adhesive layer of the tape and thereby cause particles of adhesive to remain on the wafer surface when the tape is removes.

Abstract: A method of etching multiple films with a dual layer hard mask wherein one layer is totally removed and the other layer partially removed during deep trench etching of the silicon substrate. In particular, a method of deep trench etching silicon substrates comprising the steps of providing a semiconductor substrate capable of being etched, with HBr/NF3/He/O2, having a layer of pad dielectric disposed depositing a layer of material capable of selective removability with respect to the pad dielectric, preferably BSG; depositing a layer of material having a slower etch rate than the semiconductor substrate and the layer of material capable of selective removability with respect to the pad dielectric, preferably, silicon oxide deposited by PECVD; patterning at least one of the layers, and etching the semiconductor substrate to form a trench and removing the layer of material having a slower etch rate than the semiconductor substrate, wherein trenches are of close proximity to each other.

Abstract: Stepped photoresist profiles provide various methods of forming profiles in an underlying substrate. The stepped photoresist profiles are formed in two layers of photoresist that are disposed over the substrate. The substrate is then etched twice using a respective opening in each photoresist layer to create a stepped profile in the substrate.

Abstract: In a workpiece surface processing method and a semiconductor thin layer forming method, a reference plane (12) is set in a workpiece, the reference plane (12) is controlled to a desired shape, and then the material constituting the workpiece is removed from the surface of the workpiece (10) toward the reference plane (12) is removed. The surface processing of the workpiece can be performed with high precision while not being dependent on the thickness precision of the workpiece before the surface processing.

Abstract: A depression is produced in a substrate for a capacitor of a memory cell of the DRAM cell configuration. An insulation and a storage node of the capacitor are produced in the depression. A spacer made of silicon is produced above the storage node. A first part of the spacer is doped by inclined implantation. The spacer is patterned by utilizing the different doping of the first part of the spacer. With the aid of the patterned spacer as a mask, the storage node and the insulation are altered in such a way that the storage node directly adjoins the substrate only in a limited patch of a sidewall of the depression and is otherwise isolated from the substrate by the insulation.

Abstract: A chemical mechanical polishing (CMP) system includes a polishing device including a polishing article. The polishing device holds the semiconductor wafer and provides relative movement between the semiconductor wafer and the polishing article with a slurry therebetween. The CMP system also includes a slurry processor for processing used slurry from the polishing device and for delivering processed slurry to the polishing device. The slurry processor including a metal separator for separating metal particles, polished from the semiconductor wafer, from the used slurry. The slurry can be continuously recirculated during a CMP process without damaging and/or contaminating the layers of the semiconductor wafer.

Abstract: A retainer is used with an apparatus for polishing a substrate. The substrate has upper and lower surfaces and a lateral, substantially circular, perimeter. The apparatus has a polishing pad with an upper polishing surface for contacting and polishing the lower face of the substrate. The retainer has an inward facing retaining face for engaging and retaining the substrate against lateral movement during polishing of the substrate. The retaining face engages a substrate perimeter at more than substantially a single discrete circumferential location along the perimeter.

Abstract: A method of forming a misalignment immune antifuse is presented comprised of the following steps. A partially processed semiconductor wafer is provided, containing at least one device electrically connected to a conducting region extending almost to the wafer surface, where the conducting region is surrounded by a dielectric layer which reaches the wafer surface. A blanket layer of amorphous silicon is deposited followed by deposition of a thin blanket layer of TiN and these layers are etched down to the dielectric surface except for that above the conducting region and some of the surrounding dielectric. A thin native oxide is formed over the exposed surface of the amorphous silicon. This is followed by deposition of a thicker TIN layer and of a metallization layer, which are patterned and etched so that contact is made to the lower layers. The oxidation step is repeated so as to oxidize any amorphous silicon surface that may have been inadvertently exposed in the last etching step.

Abstract: A thermal reactor having a wafer chamber for containing at least one semiconductor wafer during processing. The thermal reactor contains a quartz window having an inward bow defining a concave outside surface.

Abstract: Process for treating a semiconductor substrate 25, polymeric etchant deposits 190, silicon lattice damage 195, and native silicon dioxide layers 185, are removed in sequential process steps. The polymeric etchant deposits 190 are removed using an activated cleaning gas comprising inorganic fluorinated gas and an oxygen gas. Silicon lattice damage 195 are etched using an activated etching gas. Thereafter, an activated reducing gas comprising a hydrogen-containing gas is used to reduce the native silicon dioxide layer 185, on the substrate 25, to a silicon layer. Subsequently, a metal layer 200 is deposited on the substrate 25 and the substrate annealed to form a metal silicide layer 205. Removal of the polymeric etchant deposits 190, the silicon lattice damage 195, and the native silicon oxide layer 185 increases the interfacial conductivity of the metal silicide layer 205 to the underlying silicon-containing substrate 25.

Abstract: A method includes placing a certain substrate within a high density plasma etcher. The etcher has a directly heatable top electrode having separately powerable inner and outer components, a biasable electrostatic chuck, and a directly heatable focus ring. Plasma etching is conducted through a mask on the substrate, using a hydrogen containing fluorocarbon chemistry, with power on both the top electrode components together totalling less than or equal to 1000 W per 200 mm of substrate diameter, with an electrostatic chuck bias power less than the total top electrode power, with the top electrode heated to greater than 100° C. and the focus ring heated to at least 200° C. Such etching is conducted into a doped oxide on the substrate substantially selective to insulating material on the substrate to form a substantially self-aligned contact opening to a substrate location beneath a doped silicon dioxide layer on the substrate. Other implementations are contemplated.

Abstract: The present invention relates to a process for the treatment of Czochralski single crystal silicon wafers to dissolve existing oxygen clusters and precipitates, while preventing their formation upon a subsequent oxygen precipitation heat treatment. The process comprises rapid thermal annealing the wafer to dissolve existing oxygen clusters and precipitates. The rapid thermal anneal is performed in an atmosphere capable of oxidizing the surface of the wafer thereby causing an inward flux of silicon self-interstitial atoms in order to reduce the number density of vacancies in the single crystal silicon to a value such that oxygen precipitates will not form if the wafer is subsequently subjected to an oxygen precipitation heat-treatment.

Abstract: An etching method in which the etch selectivity of a metal silicide film with respect to a polysilicon film can be increased when a polycide film is etched by plasma enhanced etching, is provided. This method is accomplished by repeating (a) plasma etching the metal silicide film with a plasma source power applied to an etch chamber, using etch gas ions accelerated by applying a bias power to a substrate, and (b) chemically adsorbing the etch gas ions on the metal silicide film and oxidizing the polysilicon film exposed using the etch gas ions, by continuously applying the plasma source power to the etch chamber and preventing application of the bias power applied to the substrate or applying a level of bias power at which the etch gas ions are not accelerated.

Abstract: An improved fin device used as the body of a field effect transistor (“FET”) and an improved process of making the fin device. The fin device allows for the fabrication of very small dimensioned metal-oxide semiconductor (“MOS”) FETs in the size range of micrometers to nanometers, while avoiding the typical short channel effects often associated with MOSFETs of these dimensions. Accordingly, higher density MOSFETs may be fabricated such that more devices may be placed on a single semiconductor wafer. The process of making the fin device results in an improved fully planarized device.

Abstract: The present invention relates to a cleaning solution which can reliably remove the platinum group metal (e.g. Pt or Ir) contaminants adhering on the silicon-based insulating film (e.g. silicon oxide film) formed on a semiconductor substrate and further can prevent the readhesion of the removed contaminants, as well as to a cleaning method using said cleaning solution. Since the cleaning solution consists of HPFM or SPFM which is a mixture of a hydrochloric acid-hydrogen peroxide (HPM) or sulfuric acid-hydrogen peroxide (SPM) solution with a very small amount of hydrofluoric acid, the contaminants adhering on the silicon-based insulating film can be reduced to a level lower than 1×1010 atoms/cm2.