Abstract: An apparatus for reduced-pressure gaseous phase epitaxial growth by suppressing contamination upon the machine parts constituting the rotary mechanical portion and suppressing contamination upon the semiconductor wafer by maintaining the pressure in the rotary mechanical portion to lie within a particular range, and a method of controlling the above apparatus.

Abstract: Method and apparatus for etching a silicide stack including etching the silicide layer at a temperature elevated from that used to etch the rest of the layers in order to accomplish anisotropic etch.

Abstract: An etch that provides a high oxide to photoresist selectivity in a low-pressure, high-density plasma is provided. An extremely high reverse RIE lag is achieved, wherein the etching of small high-aspect ratio openings is possible, but that of large openings is not. A high-density plasma is generated so that carbon monoxide (CO) is ionized to CO+ so that at least 1 sccm equivalent of CO+ is provided. Excited CO neutrals (CO*) are also present within the plasma. Fluorocarbon and hydrofluorocarbon gases are also provided. The excited CO neutrals scavenge free fluorine, near the wafer surface and in the large openings, increasing polymer deposition on the photoresist and in the large openings thus reduce or stop etching in those regions.

Abstract: The present applicant has discovered that the application of an etch-rate reducing liquid that selectively wets the mask can permit anisotropic wet etching. In a preferred embodiment, the application of a hydrocarbon liquid film to a masked silica surface permits wet etching of straight silica walls without undercutting the mask. It is believed that the oil selectively wets the polymer mask, but not the silica surface. The oil will thus be selectively present at the point where the mask meets the silica. Since the HF etchant does not dissolve the oil, the etching produces straight walls instead of undercutting the mask.

Abstract: A method of preparing a compound semiconductor crystal is able to dope the crystal with carbon with high reproducibility. The method includes the steps of sealing a carbon oxide gas of a predetermined partial pressure and a compound semiconductor material in a gas-impermeable airtight vessel, increasing the temperature of the vessel to melt the compound semiconductor material sealed in the vessel, and then decreasing the temperature of the vessel to solidify the melted compound semiconductor material to grow a compound semiconductor crystal containing a predetermined amount of carbon. With this method, a compound semiconductor crystal with a carbon concentration of 0.1×1015cm−3 to 20×1015cm−3 is prepared with high reproducibility.

Abstract: A method for manufacturing a laser diode using Group III nitride compound semiconductor comprising a buffer layer 2, an n+ layer 3, a cladding layer 4, an active layer 5, a p-type cladding layer 61, a contact layer 62, an SiO2 layer 9, an electrode 7 which is formed on the window formed in a portion of the SiO2 layer 9, and an electrode 8 which is formed on a portion of the n+ layer 3 by etching a portion of 4 layers from the contact layer 62 down to the cladding layer 4. One pair of opposite facets S of a cavity is formed by RIBE, and then the facets are etched by gas cluster ion beam etching using Ar gas. As a result, the facets S are flatted and the mirror reflection of the facets S is improved.

Abstract: A method of etching a platinum electrode layer disposed on a substrate to produce a semiconductor device including a plurality of electrodes separated by a distance equal to or less than about 0.3 &mgr;m and having a platinum profile equal to or greater than about 85°. The method comprises heating the substrate to a temperature greater than about 150° C., and etching the platinum electrode layer by employing a high density inductively coupled plasma of an etchant gas comprising chlorine, argon and a gas selected from the group consisting of BCl3, HBr, and mixtures thereof. A semiconductor device having a substrate and a plurality of platinum electrodes supported by the substrate. The platinum electrodes have a dimension (e.g., a width) which include a value equal to or less than about 0.3 &mgr;m and a platinum profile equal to or greater than about 85°.

Abstract: A method of etching in a plasma etching chamber having an upper electrode and a susceptor is disclosed. The method comprises: setting the upper electrode and the susceptor to a first predetermined distance; performing a first etch at the first predetermined distance for a first predetermined time; setting the upper electrode and the susceptor to a second predetermined distance; and performing a first etch at the second predetermined distance for a second predetermined time.

Abstract: In a process of cleaning a semiconductor substrate on which a polysilicon film serving as a silicon-based member and a tungsten film serving as a tungsten-based member are exposed simultaneously, there is used a cleaning fluid containing a hydroxide, a water-soluble organic solvent, a compound expressed by the following chemical formula (I) or (II) which is to serve as a silicon corrosion inhibitor, an organic compound, and at least one organic compound which is to serve as a tungsten corrosion inhibitor.

Abstract: Methods for forming openings having predetermined shapes in a substrate and apparatuses with these openings. The methods may be used to form assemblies which include the substrate with its openings and elements which are disposed in the openings. In one example of a method, each of the elements include an electrical component and are assembled into one of the openings by a fluidic self assembly process. In an particular example of a method to create such an opening, the substrate is etched through a first patterned mask and is later etched through a second patterned mask. Typically, the second patterned mask is aligned relative to the opening created by etching through the first patterned mask and has an area of exposure which is smaller than an area of exposure through the first patterned mask.

Abstract: An improved method for making a semiconductor device is described. Initially, a structure is formed that includes first and second hard masking layers that cover a dielectric layer. A layer of photoresist is deposited and patterned to expose part of the second hard masking layer to define a via. That exposed part of the second hard masking layer is then etched. A second layer of photoresist is deposited and patterned to expose a second part of the second hard masking layer to define a trench. After etching the exposed second part of the second hard masking layer, a via and trench are etched into the dielectric layer, which are then filled with a conductive material.

Abstract: A method for forming on a substrate employed within a microelectronics fabrication a planarized inter-level metal dielectric (IMD) layer employing spin-on-glass (SOG) dielectric material, with attenuated etching damage to underlying layers. There is provided a substrate upon which is formed a patterned microelectronics layer over which is formed an inter-level metal dielectric (IMD) layer comprising a first silicon oxide dielectric layer and a second spin-on-glass (SOG) dielectric layer. The IMD layer is then planarized by plasma etchback method employing an etch cycle interrupted by an inert gas flushing step and substrate backside cooling by helium gas to control substrate temperature and etching reaction rates, resulting in attenuated damage to underlying layers resulting from over-etching of the IMD layer.

Abstract: A slurry for polishing a metal film of a semiconductor device, comprising alumina-type fine particles having specific properties and composition, a polishing accelerator and water.

Abstract: The present invention is directed to a method of manufacturing a trench type semiconductor element isolation structure including the steps of: (i) forming a silicon oxide film on a silicon substrate and forming a silicon nitride film on the silicon oxide film; (ii) forming a groove penetrating the silicon nitride film and the silicon oxide film, said groove reaching an interior of the silicon substrate; (iii) forming a thermal oxide film on an inner wall of said groove; (iv) depositing an oxide in said groove; (v) subjecting said oxide to a polishing treatment with the silicon nitride film used as a stopper layer, so that a part of the insulator is removed; (vi) etching the oxide by a predetermined amount of said oxide after completing the step (v); (vii) etching the silicon nitride film after completing the step (vi); and (viii) etching the silicon oxide film after completing the step (vii).

Abstract: A method of forming a micro structure having nano-sized surface features is provided. The method includes the steps of forming a micro structure having predetermined size and shape on a substrate, coating a carbon polymer layer on the substrate including the micro structure to a predetermined thickness, performing a first etch on the carbon polymer layer by means of plasma etching using a reactive gas in which O2 gas for etching the carbon polymer layer and a gas for etching the micro structure are mixed and forming a mask layer by the residual carbon polymer layer on the surface of the micro structure, and performing a second etch by means of plasma etching using the mixed reactive gas to remove the mask layer and etch the surface of the micro structure not covered by the mask layer so that the micro structure has nano-sized surface features.

Abstract: A method of forming a gate electrode in a semiconductor device which can prevent abnormal oxidation of a titanium silicide layer when performing gate re-oxidation process after a gate electrode having a stacked structure of a doped polysilicon layer and the titanium silicide layer.

Abstract: The present invention provides a method for modifying a C4 device, the device including a circuit, a polyimide layer, and a plurality of solder bumps in the active region of the C4 device. The method includes removing the polyimide layer using a plasma etch, the plasma etch comprising a mixture of oxygen and an inert gas; modifying the circuit; and cleaning the modified C4 device with a reactive flux. By mixing the oxygen with an inert gas, the oxidation of the solder bumps due to the plasma etch are reduced. Because the top layer features are now readily visible, circuit structures are more easily located, and modification can be more easily performed and with more accuracy. In the preferred embodiment, the device is then cleaned with a reactive flux, which removes any oxidation layer which has formed on the solder bumps. In this manner, circuit modification may be performed more quickly while also minimizing the oxidation of the solder bumps.

Abstract: The present invention provides fluid compositions for use in the planarization of a substrate surface. Fluid compositions include a planarization slurry having an abrasive component and a chemically interactive component and an effective amount of at least one crown ether that is capable of isolating at least one charged ion contaminant specie in the planarization slurry. Also included are fluid compositions that are pre-treated with an effective amount of at least one crown ether to remove one or more charged ion contaminants in the fluid composition utilized in a planarization process. Methods of using the fluid compositions are also provided.

Abstract: A method and system for processing a substrate in the presence of high purity C5F8. When processing oxides and dielectrics in a gas plasma processing system, C5F8 is used in combination with a carrier gas (e.g., Ar) and one or more of CO and O2. When using a silicon nitride (SixNy) layer as an etch stop, effective etching is performed due to the selectivity of oxides versus silicon nitride. The method is used when etching down to self-aligning contacts and other layers. The method may be practiced with or without using an anti-reflective coating underneath the photoresist layer.

Abstract: An object of the present invention is to provide a method of suppressing convection of a fluid in a cylindrical vessel by means of realizing an environment under micro gravity which can be maintained for such a long time that growth of a large-sized crystal be economically effected. The feature of the present invention consists in a method of suppressing occurrence of natural convection of a fluid in a cylindrical vessel, when a density gradient due to difference in temperature, concentration or partial pressure is added to the gas or liquid filled in the cylindrical vessel along the central axis of the vessel, characterized by maintaining horizontal the vessel and rotating it around the central axis.